SAB82538 Datasheet, PDF (39/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
The structure of the interrupt status registers is shown in figure 14.
Figure 14
ESCC8 Interrupt Status Registers
Each interrupt indication of registers ISR0, ISR1 and PIS can be selectively masked by
setting the corresponding bit in the corresponding mask registers IMR0, IMR1 and PIM.
Use of these registers depends on the selected serial mode. GIS, the non-maskable
Global Interrupt Status Register serves as pointer to pending channel related interrupts
and universal port interrupts.
2.2.3.1 Priority Structure
The ESCC8 has a two level priority structure with different classifications
(refer to figure 15):
First level: Type classification
All types of interrupt sources are divided into four groups with fixed priority levels.
Group 0 (highest priority): includes the Receive Pool Full interrupts of all channels.
…
Group 3 (lowest priority): refers to all other interrupt sources of all channels except those
of group 0...2. Examples: Timer interrupt, Transmit FIFO Overflow interrupt,…
Semiconductor Group
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