SAB82538 Datasheet, PDF (87/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
q Restrictions for frequency ratios between receive frequency (fr), transmit frequency
(fx) and master clock frequency (fm):
Normal mode; clock mode 0, 2a, and 6a: fr/fx < 3 (*)
Master clock mode: fm/fx ≥ 2.5 for clocks (fm and fx) with about 50 % (± 5 %) duty
cycle (*);
fr/fm < 3 (**)
(*) for unsymmetrical clocks higher ratios have to be provided, for example:
fm (high time) fm (low time) fx (high time) fx (low time) ratio
50 %
50 %
70 %
30 %
>4
50 %
50 %
75 %
25 %
>5
(**) reduced to 1.5 if receive address is pushed to RFIFO in HDLC/SDLC mode.
There are no restrictions on the relative phases of the clocks. The conditions are valid
independent of strobe signals or time-slot widths: i.e. in normal mode clock mode 1
always fulfils the condition, irrespective of how receive and transmit data are strobed.
Thus, by using strobes the above condition may always be fulfilled irrespective of the
net data rates.
q If one of the clock modes 0b, 4, 6 or 7 or the master clock is selected the internal
oscillator (OSC) is enabled which allows connection of an external crystal to pins
XTAL1-XTAL2. The output signal of the OSC can be used for one serial channel, or
for all serial channels (independent baud rate generators and DPLLs). Moreover,
XTAL1 alone can be used as input for an externally generated clock.
2.6.2 Clock Recovery (DPLL)
The ESCC8 offers the advantage of recovering the received clock from the received data
by means of internal DPLL circuitry, thus eliminating the need to transfer additional clock
information via the serial link. For this purpose, the DPLL is supplied with a “reference
clock” from the BRG which is 16 times the nominal data clock rate (clock mode 2, 3a, 6,
7a). The transmit clock may be obtained by dividing the output of the BRG by a constant
factor of 16 (clock mode 2b, 6b; bit SSEL in CCR2 set) or also directly from the DPLL
(clock mode 3a, 7a).
The main task of the DPLL is to derive a receive clock and to adjust its phase to the
incoming data stream in order to enable optimal bit sampling.
The mechanism for clock recovery depends on the selected data encoding (refer to
chapter 2.6.4).
Semiconductor Group
87