SAB82538 Datasheet, PDF (102/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
3.2 Initialization
After Reset the CPU has to write a minimum set of registers and an optional set
dependent on the required features and operating modes.
First, the serial mode, the configuration of the serial port and the clock mode have to be
defined via the CCR0 and CCR1 registers. The clock mode must be set before power-
up (CCR1). The CPU may switch the ESCC8 between power-up and power-down mode.
This has no influence upon the contents of the registers, i.e. the internal state remains
stored. In power-down mode however, all internal clocks and the oscillator circuitry are
disabled, no interrupts are forwarded to the CPU (interrupts of universal port excluded).
This state can be used as a standby mode, when the ESCC8 is temporarily not used,
thus substantially reducing power consumption.
The ESCC8 should usually be initialized in Power-Down mode.
The need for programming further registers depends on the selected features (serial
mode, clock mode specific features, operating mode, address mode, user demands).
Table 6 gives an overview about initialization of the control registers.
Table 6
Initialization of ESCC8
Item
Clock Mode
Clock mode specific features
Serial Mode
Serial Port Configuration
Registers
CCR0, CCR1
BGR, CCR2
TSAR, TSAX
XCCR, RCCR
CCR0
CCR0
CCR1
CCR2
Comment
for Master clock mode
for clock modes 2, 3, 4, 6, 7
for clock mode 5
encoding
output driver select
data inversion, RxD ↔ T×D
Semiconductor Group
102