SAB82538 Datasheet, PDF (160/253 Pages) Infineon Technologies AG – ICs for Communications

RTS…
TRS…
TLP…
SAB 82538
SAF 82538
ASYNC Mode
Request To Send
Defines the state and control of RTS pin.
0… The RTS pin is controlled by the ESCC8 autonomously.
RTS is activated when data transmission starts and deactivated when
transmission is completed.
1… The RTS pin is controlled by the CPU.
If this bit is set, the RTS pin is activated immediately and remains
active till this bit is reset.
Timer Resolution
Selects the resolution of the internal timer (factor k, see description of TIMR
register):
0…k = 32 768
1…k = 512
Test Loop
Input and output of the ASYNC channels are internally connected.
(e.g. transmitter channel 0 - receiver channel 0)
Timer Register (READ/WRITE)
7
TIMR
CNT
VALUE
0
(offset: 23)
VALUE…
(5 bits) sets the time period t1 as follows:
t₁ = k × (VALUE + 1) × TCP
where
– k is the timer resolution factor which is either 32 768 or 512 clock cycles
dependent on the programming of TRS bit in MODE.
– TCP is the clock period of transmit data.
CNT…
(3 bits)
CNT plus VALUE determine the time period t₂ after which a timer interrupt
will be generated. The time period t₂ is
t₂ = 32 × k × CNT × TCP + t₁.
If CNT is set to 7, a timer interrupt is periodically generated after the
expiration of t₁.
Semiconductor Group
160