SAB82538 Datasheet, PDF (132/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
HDLC Mode
ODS…
Output Driver Select
Defines the function of the transmit data pin (T × D)
0… T × D pin is an open drain output.
1… T × D pin is a push-pull output.
Note: This feature is also valid for pin R × D if it is switched to T × D
function via bit CCR2.SOC1.
ITF/OIN…
Interframe Time Fill / One Insertion
The function of this bit depends on the selected Serial Port Configuration
(bit SC1):
• Point-to-point configurations: ITF
Determines the idle (= no data to send) state of the transmit data pin T × D
0… Continuous logical “1” is output
1… Continuous FLAG sequences are output (“01111110” bit patterns)
• Bus configurations: OIN
When this bit is set, a “ONE” insertion (deletion) mechanism is activated:
a “1” is inserted after seven consecutive “0”s in the transmit data stream
and a “1” is deleted after seven consecutive “0” in the receive data stream.
Similar to the HDLC bit-stuffing mechanism (inserting a “0” after five
consecutive “1”s), this enables clock information to be recovered from the
receive data stream by means of a DPLL even in the case of NRZ
encoding, because a transition at bit cell boundary occurs at least every
7 bits. The “One Insertion” cannot be used in conjunction with the master
clock option.
Note: In bus configurations, the ITF is implicitly set to 0, i.e. continuous “1”s
are transmitted, and data encoding is NRZ.
CM2 – CMO… Clock Mode
Selects one of 8 different clock modes:
000 clock mode 0
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•
•
•
•
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111 clock mode 7
Semiconductor Group
132