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| SAB82538 Datasheet, PDF (173/253 Pages) Infineon Technologies AG – ICs for Communications | |||
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Receive Channel Capacity Register (WRITE)
This register is only used in clock mode 5!
Value after RESET: 00H
7
RCCR RBC7
SAB 82538
SAF 82538
ASYNC Mode
0
RBC0 (offset: 33)
RBC7â RBC0⦠Receive Bit Count, Bit 7-0
Defines the number of bits to be received within a time-slot:
Number of bits = RBC + 1 (1â¦256 bits/time-slot).
Version Status Register (READ)
7
VSTR
CD DPLA 0
0 VN3
0
VN0 (offset: 34)
CDâ¦
Carrier Detect
This bit reflects the state of the CD pin.
1⦠CD active
0⦠CD inactive
DPLAâ¦
DPLL Asynchronous
This bit is only valid when the receive clock is supplied by the DPLL and
FM0, FM1 or Manchester data encoding is selected.
It is set when the DPLL has lost synchronization. Reception is disabled
(IDLE is inserted) until synchronization has been regained. Additionally,
transmission is interrupted, too, if the transmit clock is derived from the
DPLL (same effect as the deactivation of pin CTS).
VN3â VN0⦠Version Number of Chip
0⦠Version 1
1⦠Version 2
Semiconductor Group
173
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