SAB82538 Datasheet, PDF (217/253 Pages) Infineon Technologies AG – ICs for Communications

Port Interrupt Status Register Port A...D (READ)
7
PISA
PIS7
SAB 82538
SAF 82538
BISYNC Mode
0
PIS0 (03D/07D)
PISB
PIS7
PIS0 (0BD/0FD)
PISC
PIS7
PIS0 (13D/17D)
PISD
0
0
0
0 PIS3
PIS0 (1BD/1FD)
Each PIS register is accessible via two channel addresses.
Each of the above bits is assigned to the corresponding Universal Port pin with the same
number (e.g. PISA.0 to pin PA0). Bit PISn is set and an interrupt is generated on INT if
– the corresponding Universal Port pin Pn is defined as input via register PCR and
– the interrupt source is enabled by resetting the corresponding interrupt mask PIMn in
register PIM and
– a state transition has occurred on pin Pn. For definite detection of a real state
transition, pulse width should not be shorter than 20 ns.
Note: Bits PISn are reset when register PIS is read. Masked interrupts are not normally
indicated when PIS is read. Instead, they remain internally stored and pending. A
pending interrupt is generated when the corresponding mask bit is reset to zero.
However, if bit IPC.VIS is set to “1”, interrupt statuses in PIS may be flagged
although they are masked via register PIM. These masked interrupt statuses
neither generate an interrupt vector or a signal on INT, nor are visible in register
GIS.
If more than one consecutive state transitions occur on the same pin before the
PIS register is read, only one interrupt request will be generated.
Semiconductor Group
217