SAB82538 Datasheet, PDF (156/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
ASYNC Mode
DMA Mode
Selected if DMA bit in XBCH is set.
Prior to any data transfer, the actual byte count to be transmitted must be written to the
XBCH, XBCL registers by the user. Correct transmission of data in the case of word
access and of an odd number of bytes specified in XBCH, XBCL is guaranteed.
If data transfer is then initiated via the CMDR register (command XF), the ESCC8
autonomously requests the correct amount of block data transfers (n×BW + REST;
BW = 32, 16; n = 0, 1,…).
Note: Addresses within the 32-byte address space of the FIFO all point to the same
byte/word, i.e. current data can be accessed with any address within the valid
range.
Status Register (READ)
7
0
STAR XDOV XFW RFNE FCS TEC CEC CTS 0 (offset: 20)
XDOV…
XFW…
RFNE…
FCS…
Transmit Data Overflow
More than 32 bytes have been written to the XFIFO.
This bit is reset by:
– a transmitter reset command XRES
– or when all bytes in the accessible half of the XFIFO have been moved
in the inacessible half.
Transmit FIFO Write Enable
Data can be written to the XFIFO.
RFIFO Not Empty
This bit is set if the accessible part of RFIFO holds at least one valid byte.
Flow Control Status
If in-band flow control is enabled via bit MODE.FLON, this status bit
indicates the current state of the transmitter:
0… The transmitter is in XON state, i.e. transmission is enabled or running.
1… The transmitter is in XOFF state, i.e. transmission is stopped and
disabled until an XON character is detected by the receiver.
Semiconductor Group
156