SAB82538 Datasheet, PDF (31/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Daisy Chaining
If selected via IPC register the Interrupt Enable pins IE0, IE1 are used for building a
Daisy Chain by connecting the Interrupt Enable Output (IE0) of the higher priority device
to the Interrupt Enable Input (IE1) of the lower priority device. The highest priority device
has IE1 pulled high (refer to figure 9 and 10). IE2 is unused and has to be fixed to “0”
or “1”.
Figure 9
Interrupt Cascading (Daisy Chaining) in Intel Bus Mode
For Intel type microprocessor systems the 2-cycle interrupt acknowledge scheme is
supported (’86 mode). Maximum available settling time for the chain: from the beginning
of the first INTA cycle to the beginning of the second.
Semiconductor Group
31