SAB82538 Datasheet, PDF (48/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Masked interrupt statuses are only stored internally and they become visible when the
mask is withdrawn.
In version 2 upward, an additional mode can be selected via bit IPC.VIS.
In this mode, masked interrupt status bits still neither generate an interrupt at pin INT nor
generate an interrupt vector nor are visible in GIS, but are displayed in the respective
interrupt status register(s) ISR0_0..7, ISR1_0..7 and PISA..D.
This mode is useful when some interrupt status bits are to generate an interrupt vector
and other status bits are to be polled in the individual interrupt status registers.
Notes:
q In the visible mode, all active interrupt status bits, whether the corresponding actual
interrupt is masked or not, are reset when the interrupt status register is read. Thus,
when polling of some interrupt status bits is desired, care must be taken that
unmasked interrupts are not lost in the process.
q All unmasked interrupt statuses are treated as before.
q Please note that whenever polling is used, all interrupt status registers concerned
have to be polled individually (no “hierarchical” polling possible), since GIS only
contains information on actually generated - i.e. unmasked-interrupts.
Semiconductor Group
48