SAB82538 Datasheet, PDF (200/253 Pages) Infineon Technologies AG – ICs for Communications

TCDE…
SAB 82538
SAF 82538
BISYNC Mode
by the CPU. To indicate that this RFIFO pool can be released, an RMC
command has to be issued.
Termination Character Detection Enable
When this bit is set, the received data stream is monitored for “termination
character” (TCR register). When such a character occurs, the TCD interrupt
is generated if enabled via mask register IMR0. The number of bytes to be
read from RFIFO is determined by the value of RBCL.
Receive Byte Count Low (READ)
7
RBCL RBC7
0
RBC0 (offset: 2A)
Indicates the number of valid bytes available in the accessible part of the RFIFO. This
register must be read by the CPU following a TCD interrupt. In case of a TCD interrupt
the number of valid bytes in the accessible part of the RFIFO can be evaluated by
“AND”-ing the contents of RBCL with: threshold level (bytes) – 1.
Threshold Level
Mask
4
03_H
16
0F_H
32
1F_H
RBC is reset with RMC after preceeding TCD interrupt.
In case of RPF interrupt RBC is incremented by “threshold level (bytes)”.
Transmit Byte Count Low (WRITE)
7
XBCL XBC7
0
XBC0 (offset: 2A)
Together with XBCH (bits XBC11…XBC8) this register is used in DMA Mode only, to
program the length (1…4096 bytes) of the next data block to be transmitted.
In terms of the value xbc, programmed in XBC11…XBC0 (xbc = 0…4095), the length of
the block in number of bytes is:
length = xbc + 1.
This allows the ESCC8 to request the correct amount of DMA cycles after an XF
command in CMDR.
Semiconductor Group
200