SAB82538 Datasheet, PDF (68/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Transmission of Frames
Sending frames is only possible in the Active On Loop state. Here, transmission can start
with the XTF command. If necessary, Flags as Interframe Timefill are inserted before the
current frame begins (the modified EOP and the first Flag may share a “0”). After
finishing frame transmission, Flags as Interframe Timefill are again sent until the “Go
Active On Loop” command (GALP) is reset. By returning to On Loop state an EOP
sequence is formed, the transmitter is disabled and R×D is connected to T×D again with
one bit delay.
Note: XTF or XIF may be issued before the Active On Loop state is reached. In this
case, transmission starts immediately after entering the Active On Loop state.
The opening Flag of the first frame is sent out immediately following after the
modified EOP sequence (both may share a “0”).
2.3.4 Special Functions
2.3.4.1 Shared Flags
The closing Flag of a previously transmitted frame simultaneously becomes the opening
Flag of the following frame if there is one to be transmitted. The Shared Flag feature is
enabled by setting bit SFLG in control register CCR1.
2.3.4.2 Preamble Transmission
If enabled via register CCR3, a programmable 8-bit pattern (register PRE) is transmitted
with a selectable number of repetitions after Interframe Timefill transmission is stopped
and a new frame is ready to be sent out.
Note: Zero Bit Insertion is disabled during preamble transmission. To guarantee correct
function the programmed preamble value should be different from Receive
Address Byte values defined for any of the connected stations.
2.3.4.3 CRC-32
In HDLC/SDLC mode, error protection is done by CRC generation and checking.
In standard applications, CRC-CCITT algorithm is used. The Frame Check Sequence at
the end of each frame consists of two bytes of CRC checksum.
If required, the CRC-CCITT algorithm can be replaced by the CRC-32 algorithm,
enabled via register CCR2. In this case the Frame Check Sequence consists of four
bytes.
Semiconductor Group
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