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| SAB82538 Datasheet, PDF (183/253 Pages) Infineon Technologies AG – ICs for Communications | |||
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SAB 82538
SAF 82538
Interrupt Mask Register 0, 1 (WRITE)
Value after RESET: FFH, FFH
7
ASYNC Mode
0
IMR0
TCD TIME PERR FERR PLLA CDSC RFO RPF (offset: 3A)
IMR1
BRK BRKT ALLS XOFF TIN CSC XON XPR (offset: 3B)
Each interrupt source can generate an interrupt signal at port INT (characteristics of the
output stage are defined via register IPC). A â1â in a bit position of IMR0 or IMR1 sets
the mask active for the interrupt status in ISR0 or ISR1. Masked interrupt statuses
neither generate an interrupt vector or a signal on INT, nor are they visible in register
GIS. Moreover, they will
â not be displayed in the Interrupt Status Register if bit IPC.VIS is set to â0â
â be displayed in the Interrupt Status Register if bit IPC.VIS is set to â1â.
Note: After RESET, all interrupts are disabled.
Semiconductor Group
183
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