SAB82538 Datasheet, PDF (194/253 Pages) Infineon Technologies AG – ICs for Communications

Preamble Register (WRITE)
Value after RESET: 00_H
7
PRE
PR7
SAB 82538
SAF 82538
BISYNC Mode
0
PR0 (offset: 21)
This register defines the 8-bit pattern which is sent out during preamble transmission
(refer to register CCR3).
Mode Register (READ/WRITE)
Value after RESET: 00_H
7
0
MODE
0
0 SLEN BISNC RAC RTS TRS TLP (offset: 22)
Note: Unused bits have to be set to logical “0”.
SLEN...
SYN Character Length
This bit selects the length of the SYN character:
0...6 bit (MONOSYNC) / 12 bit (BISYNC)
1...8 bit (MONOSYNC) / 16 bit (BISYNC)
BISNC...
Enable Bisync Mode
0...MONOSYNC mode is enabled (6/8 bit SYN character defined via
register SYNL).
1...BISYNC mode is enabled (12/16 bit SYN character defined via registers
SYNL and SYNH). SYNL is received/transmitted first.
RAC…
Receiver Active
Switches the receiver to operational or inoperational state.
0… receiver inactive
1… receiver active
RTS…
Request To Send
Defines the state and control of RTS pin.
0… The RTS pin is controlled by the ESCC8 autonomously.
RTS is activated when data transmission starts and deactivated when
transmission is completed.
1… The RTS pin is controlled by the CPU.
If this bit is set, the RTS pin is activated immediately and remains active
till this bit is reset.
Semiconductor Group
194