SAB82538 Datasheet, PDF (36/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.2 Microprocessor Interface
2.2.1 Register Set
The communication between the CPU and the ESCC8 is done via a set of directly
accessible registers. The interface may be configured as Siemens/Intel or Motorola type
with a selectable data bus width of 8 or 16 bits.
The CPU transfers data to/from the ESCC8 (via 64 byte deep FIFOs per direction and
channel), sets the operating modes, controls function sequences, and gets status
information by writing or reading control/status registers. All accesses can be done as
byte or word accesses if enabled. If 16-bit bus width is selected, access to lower/upper
part of the data bus is determined by address line A0 and signal BHE/BLE as shown in
table 1 and 2.
Mixed Byte/Word Access to the FIFOs
Reading from or writing to the internal FIFOs (RFIFO and XFIFO of each channel) can
be done using a 8-bit (byte) or 16-bit (word) access depending on the selected bus
interface mode. In version 1 of ESCC8, byte access in the case of 16-bit bus interface
mode is allowed if not mixed with word accesses when reading from or writing to the
same pool.
In version 2.x and upwards randomly mixed byte/word access to the FIFOs is allowed
without any restrictions.
Table 1
Data Bus Access (16-Bit Intel Mode)
BHE
0
0
1
1
A0 Register Access
ESCC8 Data Pins Used
0
FIFO word access
D0 – D15
Register word access (even addresses)
1
Register byte access (odd addresses) D8 – D15
0
Register byte access (even addresses) D0 – D7
1
No transfer performed
None
Semiconductor Group
36