SAB82538 Datasheet, PDF (77/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Flow Control for Received Data
After writing a character value to register TIC (Transmit Immediate Character) its
contents are inserted in the outgoing character stream
q Immediately upon writing this register by the microprocessor if the transmitter is in
IDLE state. If no further characters (XFIFO contents) are to be transmitted, i.e. the
transmitter returns to IDLE state after transmission of TIC, an ALLS (All Sent) interrupt
will be generated.
q After the end of a character currently being transmitted if the transmitter is not in IDLE
state. This does not affect the contents of the XFIFO. Transmission of characters from
XFIFO is resumed after the contents of register TIC are shifted out.
Transmission via this register is possible even when the transmitter is in XOFF state
(however, CTS must be “low”).
The TIC register is an eight-bit register. The number of significant bits is determined by
the programmed character length (right justified). Parity value (if programmed) and
selected number of stop bits are automatically appended, similar to the characters
written in the XFIFO. The usage of TIC is independent of flow control, i.e. is not affected
by bit MODE.FLON.
To control access to register TIC, an additional status bit STAR.TEC (TIC Executing) is
implemented which signals that transmission command of currently programmed TIC is
accepted but not completely executed. Further access to register TIC is only allowed if
bit STAR.TEC is “0”.
2.4.4.3 Continuous Transmission (DMA Mode only)
If data transfer from system memory to the ESCC8 is done by DMA (DMA bit in XBCH
set), the number of characters to be transmitted is usually defined via the Transmit Byte
Count registers (XBCH, XBCL: bits XBC11…XBC0).
However, if the “Transmit Continuously” (XC) bit in XBCH is set, the byte count value is
ignored and the DMA interface of ESCC8 will continuously request for transmit data any
time 32 new characters can be stored in XFIFO.
Note: If the XC bit is reset during continuous transmission, the transmit byte count
becomes valid again, and the ESCC8 will request the amount of DMA transfers
programmed via XBC11…XBC0. Otherwise, the continuous transmission is
stopped when a data underrun condition occurs in XFIFO, i.e. the DMA controller
does not transfer further data to ESCC8. In this case continuous “1”-s (IDLE) are
transmitted.
Semiconductor Group
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