SAB82538 Datasheet, PDF (152/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
HDLC Mode
Channel Configuration Register 4 (READ/WRITE) (Version 2 upwards)
Value after RESET: 00_H
7
0
CCR4
0
0
0
0
0
0 RFT1 RFT0 (offset: 3F)
Note: Unused bits have to be set to logical “0”.
RFT1, RFT0 … RFIFO Threshold Level
The size of the accessible part of RFIFO can be determined by
programming these bits. The number of valid bytes after an RPF interrupt
is given in the following table:
RFT1
0
0
1
1
RFT0
0
1
0
1
Size of Accessible Part of RFIFO
32 bytes (RESET value)
16 bytes
4 bytes
2 bytes
The value of RFT 1,0 can be changed dynamically
– If reception is not running (recommended: receiver is disabled by setting
MODE.RAC to “0”), or
– after RME interrupt has been generated, but before the command
CMDR.RMC is issued (DMA controlled data transfer), or
– after the current data block has been read, but before the command
CMDR.RMC is issued (interrupt controlled data transfer). See Note.
Note: It is seen that changing the value of RFT1,0 is possible even during
the reception of one frame. The total length of the received frame can
be always read directly in RBCL, RBCH after an RPF interrupt,
except when the threshold is increased during reception of that
frame. The real length can then be inferred by noting which bit
positions in RBCL are reset by an RMC command (see table
below):
RFT1
0
0
1
1
RFT0
0
1
0
1
Bit Positions in RBCL Reset by a
CMDR.RMC Command
RBC4 .… 0
RBC3 … 0
RBC1,0
RBC0
Semiconductor Group
152