SAB82538 Datasheet, PDF (127/253 Pages) Infineon Technologies AG – ICs for Communications

Note 1:
Note 2:
Note 3:
SAB 82538
SAF 82538
HDLC Mode
S-frames are handled automatically and are not transferred to the
microprocessor.
For U-frames (bit 0 of RHCR = 1) the control field is as in the modulo 8 case.
For I-frames (bit 0 of RHCR = 0) the compressed control field has the same
format as in the modulo 8 case, but only the three LBS’s of the receive and
transmit counters are visible:
bit
7
6
5
4
3
2
1
0
N(R)
P
N(S)
0
Receive Address Byte Low Register 2 (WRITE)
7
RAL2
RAL2
0
(offset: 29)
Value of the second individually programmable low address byte. If a one byte address
field is selected, RAL2 is considered as the address of a RESPONSE frame according
to X.25 LAPB protocol.
Receive Byte Count Low (READ)
7
RBCL
RBC7
0
RBC0 (offset: 2A)
Together with RBCH (bits RBC11 - RBC8), indicates the length of a received frame
(1…4096 bytes). Bits RBC4-0 indicate the number of valid bytes currently in RFIFO.
These registers must be read by the CPU following a RME interrupt.
Semiconductor Group
127