XRT74L73 Datasheet, PDF (99/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
FIGURE 13. FLOW-CHART OF THE “UNI DEVICE SELECTION AND WRITE PROCEDURE” FOR THE MULTI-PHY OPERATION.
START
Poll all UNIs within the “Multi-PHY” System
Determine which UNIs are “Available”
Select “Available” UNI
1. Apply Utopia Address of the Transmit Utopia
Interface block onto the “Utopia Address” bus
2. Negate the TxEnB* signal
Begin writing ATM cell data into “Selected” UNI
1. Assert TxEnB*
2. Place first byte/word of ATM cell onto the “Transmit
Utopia Data Bus & Assert TxSoC
Continue to write ATM Cell data
Is
TxClav
No
“High”
?
Yes
Wait for TxClav to toggle “high”
No
Is
there any more
Yes
ATM cell data to be
Is
TxClav
No
written to selected
“High”
UNI?
?
Yes
Check the TxClav level after
writing 48 bytes of cell data
Figure 14 presents a timing diagram that illustrates
the behavior of various “Transmit UTOPIA Interface
block” signals during the “Multi-PHY” UNI Device
Selection and Write operation.
FIGURE 14. TIMING DIAGRAM OF THE TRANSMIT UTOPIA DATA AND ADDRESS BUS SIGNALS, DURING THE
“MULTI-PHY” UNI DEVICE SELECTION AND WRITE OPERATIONS.
1
2
3
4
5
6
7
8
9
10
11
12
TxUClk
TxUAddr [4:0] _{00h 1Fh 02h 1Fh}
TxUClav
TxUEn
00h
02h
Cell Transmitted to 02h
TxUData [15:0] _{W23 W24 W25 W26}
TxUSoC
00h 02h 1Fh 00h 02h 1Fh
00h
02h
00h
02h
Cell Transmitted to 00h
W0
W1
W2
W3
W4
02h 00h
02h
W5
W6
Note: regarding Figure 14
100