XRT74L73 Datasheet, PDF (198/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
clock signal. The Teriminal Equipment will receive
the 11.184MHz clock signal via the
DS3_Nib_Clock_In input pin. The XRT74L73 will out-
put the 11.184MHz clock signal via the TxNibClk out-
put pin.
The Terminal Equipment will serially output the data
on the DS3_Data_Out[2:0] pins upon the rising edge
of the signal at the DS3_Clock_In input pin. The
XRT74L73 will latch the data, residing on the Tx-
Nib[2:0] input pins, on the rising edge of the TxNibClk
signal.
In this case the XRT74L73 has the responsibility of
providing the framing reference signal by pulsing the
TxFrame output pin (and in turn the
Tx_Start_of_Frame input pin of the Terminal Equip-
ment) "High" for one nibble-period, coincident with
the last nibble within a given DS3 frame.
Finally, the XRT74L73 will always internally generate
the Overhead bits, when it is operating in both the
DS3 and Nibble-parallel modes. The XRT74L73 will
pull the TxOHInd input pin "Low".
The behavior of the signals between the XRT74L73
and the Terminal Equipment for DS3 Mode 6 Opera-
tion is illustrated in Figure 62 .
FIGURE 62. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L73 AND THE TERMINAL
EQUIPMENT (DS3 MODE 6 OPERATION)
Terminal Equipment Signals
TxInClk
DS3_Nib_Clock_In
DS3_Data_Out[3:0]
Tx_Start_of_Frame
Nibble [1175]
Nibble [0]
XRT72L5x Transmit Payload Data I/F Signals
TxInClk
TxNibClk
TxNib[3:0]
TxNibFrame
Nibble [1175]
Nibble [0]
Note: TxNibFrame pulses high to denote
DS3 Frame Boundary.
DS3 Frame Number N
DS3 Frame Number N + 1
Sampling Edge of the XRT72L5x Device
How to configure the XRT74L73 into Mode 6
1. Set the NibInt input pin "High".
2. Set the TimRefSel[1:0] bit-fields (within the
Framer Operating Mode Register) to 1X as illus-
trated below.
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