XRT74L73 Datasheet, PDF (86/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
Register, as depicted below.
UTOPIA Configuration Register: Address = 6Ah
BIT 7
BIT 6
Unused
RO
BIT 5
Handshake Mode
R/W
BIT 4
M-PHY
R/W
BIT 3
CellOf52 Bytes
R/W
BIT 2
BIT 1
TFIFODepth[1, 0]
R/W
BIT 0
UtWidth16
R/W
The following table specifies the relationship between
the value of this bit and the number of octets/cell that
the Transmit UTOPIA Interface block will process.
TABLE 4: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 3 (CELLOF52BYTES) WITHIN THE UTOPIA
CONFIGURATION REGISTER, AND THE NUMBER OF OCTETS PER CELL THAT WILL BE PROCESSED
BY THE TRANSMIT AND RECEIVE UTOPIA INTERFACE BLOCKS.
CELLOF52 BYTES
0
1
NUMBER OF BYTES/CELLS
53 bytes when the UTOPIA Data Bus width is 8 bits.
54 bytes when the UTOPIA Data Bus width is 16 bits.
52 bytes, regardless of the configured width of the UTOPIA Data Bus
Note: This selection applies to both the Transmit UTOPIA
and Receive UTOPIA interface blocks. Additionally, the
shaded selection reflects the default condition upon power
up or reset.
2.1.2.1.3Parity Checking and Handling of ATM
Cell Data received from the ATM
Layer Processor
The ATM Layer processor is expected to compute the
odd parity bit for all bytes or words that it intends to
write into the Transmit UTOPIA Interface block. The
ATM Layer processor is then expected to apply the
value of this parity bit to the TxUPrty input pin of the
UNI, while the corresponding byte (or word) is
present on the Transmit UTOPIA data bus. The
Transmit UTOPIA Interface block will independently
compute the odd parity of the contents on the Transmit
UTOPIA Data Bus. Afterwards, the Transmit UTOPIA
Interface block will compare its calculated value for
parity with that placed on the TxUPrty input pin (by
the ATM Layer processor). If these two values are
equal, then the byte (or word) of data will be pro-
cessed through the Transmit UTOPIA Interface block.
However, if these two parity values are not equal,
then the “Detection of Parity Error (Transmit UTOPIA
Interface)” interrupt will occur, and the cell comprising
this errored byte (or word) will be (optionally) discard-
ed. The Transmit UTOPIA Interface block can be con-
figured to discard or retain this “errored” cell by writ-
ing the appropriate data to the Transmit UTOPIA In-
terrupt/Status Register (Address = 6Eh) as depicted
below.
Transmit UTOPIA Interrupt/Status Register (Address = 6Eh)
BIT 7
BIT 6
TFIFO Reset
Discard Upon
PErr
R/W
R/W
BIT 5
TPerr IntEn
R/W
BIT 4
TFIFO
ErrIntEn
R/W
BIT 3
BIT 2
BIT 1
TCOCA IntEn
TPErr IntStat
TFIFO” Over-
Int Stat
R/W
RUR
RUR
BIT 0
TCOCA
IntStat
RUR
If this bit is set to a “1”, then the Transmit UTOPIA In-
put Interface block will discard the errored cell. If this
bit-field to is set to “0”, then the Transmit UTOPIA In-
terface block will not discard the errored cell and this
cell will be written into the TxFIFO.
2.1.2.2Transmit UTOPIA FIFO Manager
The TxFIFO Manager has the following responsibilities.
• Monitoring the fill level of the TxFIFO, and providing
the appropriate level of Flow Control of data
between the Transmit UTOPIA Interface block and
the ATM Layer processor.
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