XRT74L73 Datasheet, PDF (98/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
FIGURE 12. TIMING DIAGRAM ILLUSTRATING THE BEHAVIOR OF VARIOUS SIGNALS FROM THE ATM LAYER PROCESSOR
AND UNI, DURING POLLING.
1
2
3
4
5
6
7
8
9
10
11
12
TxUClk
TxUAddr [4:0] 00h 1Fh
TxUClav
00h
TxUEn
TxUData [15:0] W27 W0
TxUSoC
02h 1Fh
02h
00h 02h 1Fh
00h _02h
02h 00h
02h
1Fh
00h
00h 02h
00h
W1
W2 W3
W4
W5
W6 W7
W8
W9 W10
Note: regarding Figure 12
1. The Transmit UTOPIA Data Bus is configured to be
16 bits wide. Hence, the data, which the ATM Layer
processor places on the Transmit UTOPIA Data
bus, is expressed in terms of 16-bit words: (e.g.,
W0–W26.)
2. The Transmit UTOPIA Interface Block is configured to
handle 54 bytes/cell. Hence, Figure 12 illustrates the
ATM Layer processor writing 27 words (W0 through
W26) for each ATM cell.
3. The ATM Layer processor is currently writing ATM cell
data to the Transmit UTOPIA Interface Block, within
UNI #1 (TxUAddr[4:0] = 00h) during this “polling pro-
cess”.
4. The TxFIFO, within UNI#2’s Transmit UTOPIA Inter-
face block (TxUAddr[4:0] = 02h) is incapable of receiv-
ing any additional ATM cell data from the ATM Layer
processor. Hence, the TxUClav line will be driven “low”
whenever this particular Transmit UTOPIA Interface
block is “polled”.
5. The Transmit UTOPIA Address of 1Fh is not associated
with any UNI device, within this “Multi-PHY” system.
Hence, the TxUClav line is tri-stated whenever this
address is “polled”.
Note: Although Figure 11 depicts connections between the
Receive UTOPIA Interface block pins and the ATM Layer
processor; the Receive UTOPIA Interface block operation, in
the Multi-PHY mode, will not be discussed in this section.
Please see Section 7.4.2.2.2.2 for a discussion on the
Receive UTOPIA Interface block during Multi-PHY opera-
tion.
2.1.2.4.2.2Writing ATM Cell Data into a Different
UNI
After the ATM Layer processor has “polled” each of
the UNI devices within its system, it must now select
a UNI, and begin writing ATM cell data to that device.
The ATM Layer processor makes its selection and
begins the writing process by:
1. Applying the UTOPIA Address of the “target” UNI on
the “UTOPIA Address Bus”.
2. Negate the TxUEn signal. This step causes the
“addressed” UNI to recognize that it has been selected
to receive the next set of ATM cell data from the ATM
Layer processor.
3. Assert the TxUEn signal.
4. Assert the TxUSoC input pin.
5. Begin applying the ATM Cell data in a byte-wide (or
word-wide) manner to the Transmit UTOPIA Data
Bus.
Figure 13 presents a flow-chart that depicts the “UNI
Device Selection and Write” process in Multi-PHY op-
eration.
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