XRT74L73 Datasheet, PDF (444/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
plished by periodically reading the PMON Framing
Bit/Byte Error Event Count Registers (Address =
0x52 and 0x53). The byte format of these registers
are presented below.
6.3.2.5 The RxOOF and RxLOF output pin.
The user can roughly determine the current framing
state that the Receive E3 Framer block is operating in
by reading the logic state of the RxOOF and the Rx-
LOF output pins. Table 101 presents the relation-
ship between the state of the RxOOF and RxLOF
output pins, and the Framing State of the Receive E3
Framer block.
TABLE 101: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE
FRAMING STATE OF THE RECEIVE E3 FRAMER BLOCK
RXLOF
0
0
1
1
RXOOF
FRAMING STATE OF THE RECEIVE E3 FRAMER BLOCK
0
In Frame
1
OOF Condition (The Receive E3 Framer block is operating in the 3ms OOF period).
0
Invalid
1
LOF Condition
6.3.2.6 E3 Receive Alarms
6.3.2.6.1 The Loss of Signal (LOS) Alarm
Declaring an LOS Condition
The Receive E3 Framer block will declare a Loss of
Signal (LOS) Condition, when it detects 32 consecu-
tive incoming “0’s” via the RxPOS and RxNEG input
pins or if the ExtLOS input pin (from the XRT7300
DS3/E3/STS-1 LIU IC) is asserted. The Receive E3
Framer block will indicate that it is declaring an LOS
condition by.
• Asserting the RxLOS output pin (e.g., toggling it
“High”).
• Setting Bit 4 (RxLOS) of the Rx E3 Configuration &
Status Register to “1” as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Rx LOF Algo RxLOF
RxOOF
RxLOS
RxAIS
RxPld Unstab
Rx
TMark
RxFERF
R/W
RO
RO
RO
RO
RO
RO
RO
0
0
0
1
0
0
0
0
• The Receive E3 Framer block will generate a
Change in LOS Condition interrupt request. Upon
generating this interrupt request, the Receive E3
Framer block will assert Bit 1 (LOS Interrupt Status
within the Rx E3 Framer Interrupt Status Register -
1, as depicted below.
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
COFA
Interrupt
Status
OOF
Interrupt
Status
RO
RO
RO
RUR
RUR
0
0
0
0
0
BIT 2
LOF
Interrupt
Status
RUR
0
BIT 1
LOS
Interrupt
Status
RUR
1
BIT 0
AIS
Interrupt
Status
RUR
0
Clearing the LOS Condition
The Receive E3 Framer block will clear the LOS con-
dition when it encounters a stream of 32 bits that
does not contain a string of 4 consecutive zeros.
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