XRT74L73 Datasheet, PDF (170/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
cell data that needs to be read, at any given time. The
manner in which the ATM Layer processor “polls” its
UNI devices follows.
FIGURE 43. AN ILLUSTRATION OF MULTI-PHY OPERATION WITH UNI DEVICES #1 AND #2
TxUData [15:0]
TxUAddr [4:0]
TxUPrty
TxUEn
TxUSoC
TxUClav
RxUData [15:0]
RxUAddr [4:0]
RxUPrty
RxUEn
RxUSoC
UNI # 1 _RxUClav
TxAddr = 00h RxAddr = 01h
TxUData [15:0]
TxUAddr [4:0]
TxUPrty
TxUEn
TxUSoC
TxUClav
RxUData [15:0]
RxUAddr [4:0]
RxUPrty
RxUEn
RxUSoC
UNI # 2 _RxUClav
TxAddr = 02h RxAddr = 03h
TxData[15:0]
Ut_Addr[4:0]
Tx_Parity
Tx_Ut_WR*
Tx_SoC_out
TxClav_In
RxData[15:0]
Rx_Parity
Rx_Ut_Rd*
Rx_SoC_In
RxClav_In
ATM Layer Processor
Figure 43 depicts a “Multi-PHY” system consisting of
an ATM Layer processor and two (2) UNI devices,
designated as “UNI #1” and “UNI #2”. In this figure,
both of the UNIs are connected to the ATM Layer
processor via a common “Transmit UTOPIA” Data
Bus, “Receive UTOPIA” Data Bus, a common TxU-
Clav line, a common RxUClav line, as well as com-
mon TxUEn, RxUEn, TxUSoC and RxUSoC lines.
The ATM Layer processor will also be addressing the
Transmit and Receive UTOPIA Interface block via a
common “UTOPIA” address bus (Ut_Addr[4:0]).
Therefore, the Transmit and Receive UTOPIA Blocks,
of a given UNI must have different addresses; as de-
picted in Figure 42 .
The UTOPIA Address values that have been assigned
to each of the Transmit and Receive UTOPIA Interface
blocks within Figure 42 , are listed below in Table 31
.
TABLE 31: UTOPIA ADDRESS VALUES OF THE UTOPIA INTERFACE BLOCKS ILLUSTRATED IN FIGURE 43
BLOCK
Transmit UTOPIA Interface block—UNI #1
Receive UTOPIA Interface block—UNI #1
UTOPIA ADDRESS VALUE
00h
01h
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