XRT74L73 Datasheet, PDF (36/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
AD9
NAME
TxUEn/
TxPEn
AD10
TxUClk/
TxPClk
AA10
TxUClkO/
TxPClkO
TYPE
I
I
O
DESCRIPTION
Transmit UTOPIA Interface Block - Write Enable/Transmit POS-PHY Inter-
face - Write Enable:
The exact function of this input pin depends upon whether the XRT74L73 device
has been configured to operate in the ATM UNI or PPP Mode.
ATM UNI Mode Operation - TxUEn
This active-low signal, from the ATM Layer processor enables the data on the
Transmit UTOPIA Data Bus to be written into the TxFIFO on the rising edge of
TxUClk. When this signal is asserted, then the contents of the byte or word that
is present, on the Transmit UTOPIA Data Bus, will be latched into the Transmit
UTOPIA Interface block, on the rising edge of TxUClk. When this signal is
negated, then the Transmit UTOPIA Data bus inputs will be tri-stated.
PPP Mode Operation - TxPEn
This active-low signal, from the Link Layer processor enables the data on the
Transmit POS-PHY Data Bus to be written into the TxFIFO on the rising edge of
TxPClk. When this signal is asserted, then the contents of the byte or word that
is present, on the Transmit POS-PHY Data Bus, will be latched into the Transmit
POS-PHY Interface block, on the rising edge of TxPClk.When this signal is
negated, then the Transmit POS-PHY Data bus inputs will be tri-stated.
Transmit UTOPIA Interface Clock/Transmit POS-PHY Interface Clock Input:
The exact function of this input pin depends upon whether the XRT74L73 device
has been configured to operate in the ATM UNI or in the PPP Mode.
ATM UNI Mode - TxUClk
The Transmit UTOPIA Interface clock is used to latch the data on the Transmit
UTOPIA Data bus into the Transmit UTOPIA Interface block. This clock signal is
also used as the timing source for circuitry used to process the ATM cell data
into and through the TxFIFO.
During Multi-PHY operation, the data on the Transmit UTOPIA Address bus pins
is sampled on the rising edge of TxUClk.
PPP Mode - TxPClk
The Transmit POS-PHY Interface clock is used to latch the data on the Transmit
POS-PHY Data bus, into the Transmit POS-PHY Interface block. This clock sig-
nal is also used as the timing source for circuitry used to process the Packet
data into and through the TxFIFO.
Transmit UTOPIA Interface Clock/Transmit POS-PHY Interface Clock Out-
put:
This output pin is derived from an internal PLL.
37