XRT74L73 Datasheet, PDF (1/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
OCTOBER 2003
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
GENERAL DESCRIPTION
The XRT74L73 3 Channel, ATM UNI/PPP Physical
Layer Processor with integrated DS3/E3 framing con-
troller is designed to support ATM direct mapping and
cell delineation as well as PPP mapping and Frame
processing. For ATM UNI applications, this device
provides the ATM Physical Layer (Physical Medium
Dependent and Transmission Convergence sub-lay-
ers) interface for the public and private networks at
DS3/E3 rates. For Clear-Channel Framer applica-
tions, this device supports the transmission and re-
ception of “user data” via the DS3/E3 payload.
• Contains on-chip 54 byte Transmit and Receive
OAM Cell Buffer for transmission, reception and
processing of OAM Cells
• Supports ATM cell or PPP Packet Mapping
• Supports M13 and C-Bit Parity Framing Formats
• Supports DS3/E3 Clear-Channel Framing Applica-
tions
• Includes PRBS Generator and Receiver
• Supports Line, Cell, and PLCP Loop-backs
• Interfaces to 8 Bit wide Intel, Motorola, PowerPC,
and Mips µPs
The XRT74L73 DS3 ATM UNI/Clear-Channel Framer
incorporates Receive, Transmit, Microprocessor Inter-
face, Performance Monitor, Test and Diagnostic and
Line Interface Unit Scan Drive functional sections.
FEATURES
• Compliant with 8/16 bit UTOPIA Level I and II and
PPP Multi-PHY Interface Specifications and sup-
ports UTOPIA Bus operating at 25, 33 or 50 MHz
• HDLC controller per channel for Tx and Rx
• Low power 3.3V, 5V Input Tolerant, CMOS
• Available in 388 pin PBGA Package
APPLICATIONS
• Digital Access and Cross Connect Systems
• Digital, ATM, WAN and LAN Switches
• Network Interface Service Units
• Contains on-chip 16 cell FIFO (configurable in
depths of 4, 8, 12 or 16 cells), in both the Transmit
(TxFIFO) and Receive Directions (RxFIFO)
FIGURE 1. BLOCK DIAGRAM OF THE XRT74L73 ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
A[6:0]
WR_RW
RD_DS
CS
ALE_AS
Reset
INT
D[7:0]
µPClk
RDY_DTCK
Type
Type_0
Type_1
Pblast
PDBEN
TxPOS_n
TxNEG_n
TxLineClk_n
TxFrame_n
TxOHClk_n
TxOHFrame_n
TxAISEn_n
TxInClk_n
TxOHIns_n
TxOH_n
TxOHEnable_n
TxPOHFrame_n
8KRef_n
TxStuffCtl_n
TxPFrame_n
TxPOH_n
TxPOHClk_n
TxPOHIns_n
EncoDis_n
TxGFC_n
TxGFCMS_n
TxGFCClk
TxCellTxed_n
TXOHInd_n
TxNibFrame_n
TxNibClk_n
TxNib_[3:0]_n
TxFrameRef_n
TxSerData_n
TxHDLCClk_n
TxHDLCDat_[7:0]_n
SendFCS_n
SendMSG_n
TxUClk
TxUClkO
TxUData[15:0]/TxPData[15:0]
TxUPrty
TxUSoC/TxPSOP
TxUEn
TxUClav
TxUAddr[4:0]
TxPEOP
TxMod_n
TxTSX/TxPOSF
TxPERR
Microprocessor
MIinctreorpfarocceessor
(ProgIrnatmermfaacbele
Re(Pgriostgerrasmamnadble
InteRrreugpist tBerloscakn)d
Interrupt Block)
Transmitter_n
Transmitter_n
Transmit
DS3/E3
Framer
Transmit PLCP
Processor/
Clear Channel
Tx Serial Data
Processor
Note: Typical
channel (n) shown,
where;
n = 0, 1, 2 or 3.
JTAG
JTAG
FEAC
ProcFesEsAoCr
ChaPnrnoceel s(nso) r
Channel (n)
LAPD
TransLcAeiPvDer
ChTarnanneslce(niv)er
Channel (n)
Performance
PMeornfoitromrance
ChanMnoenl i(tno)r
Channel (n)
Receiver_n
Receiver_n
Receive
DS3/E3
Framer
Receive PLCP
Processor/
Clear Channel
Rx Serial Data
Processor
Receive Cell
Processor
Transmit Cell
Processor
HDLC
CONTROLLER
HDLC
CONTROLLER
Tx Utopia/PPP
Interface
Line Interface
Drive and Scan
Rx Utopia/PPP
Interface
TDI
TCK
TMS
TDO
TRST
RxLOS_n
RxOOF_n
EXTLOS_n
RxAIS_n
RxRed_n
RxOH_n
RxOHClk_n
RxLineClk_n
RxPOS_n
RxNEG_n
RxOHFrame_n
RxSerClk_n
RxOHEnable_n
RxPOOF_n
RxPFrame_n
RxPOHFrame_n
RxPOH_n
RxPOHClk_n
RxPLOF_n
RxPRed_n
RxLCD_n
RxCellRxed_n
RxGFCClk_n
RxGFCMS_n
RxGFC_n
RxClk_n
RXOHInd_n
RxFrame_n
RxNib_[3:0]_n
RxSerData_n
RxOutClk_n
ValidFCS_n
RxIdle_n
RxHDLCDat_[7:0]_n
RxHDLCClk_n
RxUClk
RxUClkO
RxUEn/RxPEnb
RxUPrty
RxUData[15:0]/RxPData[15:0]
RxUSoC/RxPSOP
RxUClav
RxUAddr[4:0]
RxMOD_n
RxPEOP
RxTSX/RxPSOF
RxPDVAL
RxPERR
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com