XRT74L73 Datasheet, PDF (429/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
FIGURE 190. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND
TXNEG ARE CONFIGURED TO BE UPDATED ON THE RISING EDGE OF TXLINECLK
t32
TxLineClk
t30
t33
TxPOS
TxNEG
FIGURE 191. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND
TXNEG ARE CONFIGURED TO BE UPDATED ON THE FALLING EDGE OF TXLINECLK
t32
TxLineClk
t31
t33
TxPOS
TxNEG
6.2.6 Transmit Section Interrupt Processing
The Transmit Section of the XRT74L73 can generate
an interrupt to the Microprocessor/Microcontroller for
the following reasons.
• Completion of Transmission of LAPD Message
6.2.6.1 Enabling Transmit Section Interrupts
As mentioned in Section 36, the Interrupt Structure,
within the XRT74L73 contains two hierarchical levels:
• Block Level
• Source Level
The Block Level
The Enable State of the Block Level for the Transmit
Section Interrupts dictates whether or not interrupts
(enabled) at the source level, are actually enabled.
The user can enable or disable these Transmit Sec-
tion interrupts, at the Block Level by writing the ap-
propriate data into Bit 1 (Tx DS3/E3 Interrupt Enable)
within the Block Interrupt Enable register (Address =
0x04), as illustrated below.
430