XRT74L73 Datasheet, PDF (105/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
Processor will then proceed to read in the contents of
the “Transmit OAM Cell” buffer, and form a cell from
this data. This OAM cell will be subsequently pro-
cessed like any user or Idle cell (e.g., processed
through the HEC Byte Calculator and Cell Scrambler)
and then routed to the Transmit PLCP Processor (or
Transmit DS3 Framer).
As mentioned earlier, the Transmit Cell Processor will
perform a “Data Path Integrity Check” on all user cells
that it reads from the TxFIFO. More specifically, the
Transmit Cell Processor will look for a specific data
pattern that should be residing within octet #5 of
these cells. The purpose of this test is to verify the in-
tegrity of the communication link throughout the “ATM
Layer processor” system. This “Data Path Integrity
Pattern” was written into the cell by the Receive Cell
Processor of another UNI, prior to its entry into the
“ATM Layer processor” system. If the Transmit Cell
Processor detects a discrepancy between the con-
tents of octet #5 and the expected pattern, then the
Transmit Cell Processor will generator a “Data Path
Integrity Check” error interrupt. After the Transmit
Cell Processor has completed checking for the “Data
Path Integrity Check” pattern; within a given cell, it will
(optionally) overwrite this pattern by inserting the
HEC byte.
The Transmit Cell Processor will inform external
circuitry when a cell has been transmitted from the
Transmit Cell Processor to either the Transmit PLCP
Processor or the Transmit DS3 Framer, by pulsing the
“TxCellTxed” output pin.
2.2.2.1HEC Byte Calculation and Insertion
The “HEC Byte Calculator” takes the first four bytes of
each cell and computes a CRC-8 value via the gener-
ating polynomial x⁸ + x² + x + 1. The user has the op-
tion to have the coset polynomial x⁶ + x⁴ + x² + 1
modulo-2 added to the CRC-8 byte and, instead in-
sert this newly computed value into byte 5 of the cell
before transmission. The following are additional op-
tions regarding the “HEC Byte Calculator”.
• HEC Byte Calculation and Insertion Enable/Disable
for user and OAM cells.
• HEC Byte Calculation and Insertion Enable/Disable
for Idle Cells.
• Inserting errors into the HEC byte, for chip/equipment test-
ing purposes.
The implementation and result of selecting each of
these options are presented below.
2.2.2.1.1Configuring the HEC Byte Calculator for
User and OAM Cells
The “HEC Byte Calculation and Insertion” feature can
be enabled or disabled for user and OAM cells. This
option is excercised by writing the appropriate value
to Bit 5 of the TxCP Control Register, as depicted be-
low.
TxCP Control Register (Address = 60h)
BIT 7
BIT 6
BIT 5
Scrambler En Coset Enable
HEC Insert
Enable
R/W
R/W
R/W
1
1
x
BIT 4
TDPChk
Pattern
R/W
1
BIT 3
GFC Insert
Enable
R/W
0
BIT 2
BIT 1
BIT 0
TDPErr Inter-
rupt Enable
Idle Cell HEC
CalEn
TDPErr Inter-
rupt
Status
R/W
R/W
RUR
0
1
0
If this feature is disable, then the HEC byte will not be
computed and the contents within the fifth octet posi-
tion of each cell (e.g., typically the “Data Path Integrity
Check” pattern) will be transmitted to the Transmit
PLCP (or Transmit DS3 Framer) block as is. The fol-
lowing table relates the content of this bit-field to the
“HEC Byte Calculator’s” handling of valid (e.g., user or
OAM) cells.
TABLE 8: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT-FIELD 5 (HEC INSERT ENABLE) WITHIN THE TXCP
CONTROL REGISTER, AND THE HEC BYTE CALCULATOR’S HANDLING OF VALID CELLS
HEC INSERT ENABLE
RESULT
0
HEC Byte Calculation is disabled and the 5th byte is transmitted to the Transmit PLCP Block (or Transmit
DS3 Framer) as is
1
The HEC Byte is calculated and is inserted into the 5th octet position of each valid cell.
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