XRT74L73 Datasheet, PDF (136/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
Receive PLCP Interrupt Enable Register
BIT 7
BIT 6
BIT 5
BIT 4
Unused
R/W
R/W
R/W
R/W
x
x
x
x
BIT 3
R/W
x
BIT 2
R/W
x
BIT 1
POOF Interrupt
Enable
R/W
0
BIT 0
PLOF Interrupt
Enable
R/W
0
To enable these interrupts write a “1” to their corre-
sponding bit-fields, in this register. Conversely, to dis-
able these interrupts write a “0” to these bit fields.
These bit-fields are “0” upon power-up or reset of the
UNI chip.
3.3Receive Cell Processor
3.3.1Brief Description of the Receive Cell
Processor
The Receive Cell Processor receives either delineated
PLCP frames from the Receive PLCP Processor, or
“Direct Mapped ATM” cells from the Receive DS3
Framer. The Receive Cell Processor will then perform
the following operations on this data.
• Cell Delineation
• HEC Byte Verification
• Idle Cell Filtering (optional)
• User/OAM Cell Filtering (optional)
• Cell-payload de-scrambling (optional)
The Receive Cell Processor will also output the GFC
Nibble value of each incoming cell, via the “Receive
GFC Nibble Field” Serial Output port.
Figure 27 presents a simple block diagram of the Re-
ceive Cell Processor block along with its external pins.
FIGURE 27. SIMPLE ILLUSTRATION OF THE RECEIVE CELL PROCESSOR, WITH ASSOCIATED PINS
From Receive E3
Framer
Receive Cell
Processor
RxCellRxed
RxGFCClk
RxGFCMSB
RxGFC
RxLCD
To Receive Utopia
Interface Block
3.3.2Functional Description of Receive
Cell Processor
The Receive Cell Processor receives delineated
frames from the Receive PLCP Processor (or ATM
Cells from the Receive DS3 Framer). Once the
Receive Cell Processor receives this information then
it will proceed to perform the following functions.
• Cell Delineation
• HEC Byte Verification (Header Error Detection/Cor-
rection)
• Idle Cell Filtering
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