XRT74L73 Datasheet, PDF (402/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
TABLE 87: THE OVERHEAD BITS WITHIN THE E3 FRAME AND THEIR POTENTIAL SOURCES
OVERHEAD BIT
TR - Bit 0
INTERNALLY GENERATED
No
ACCESSIBLE VIA THE TRANSMIT OVERHEAD
DATA INPUT INTERFACE
Yes
BUFFER/REGISTER
ACCESSIBLE
Yes
MA - Bit 7
Yes
Yes
Yes
MA - Bit 6
Yes
Yes
Yes
MA - Bit 5
Yes
Yes
Yes
MA - Bit 4
Yes
Yes
Yes
MA - Bit 3
Yes
Yes
Yes
MA - Bit 2
Yes
Yes
Yes
MA - Bit 1
Yes
Yes
Yes
MA - Bit 0
Yes
Yes
Yes
NR - Bit 7
No
Yes
Yes
NR - Bit 6
No
Yes
Yes
NR - Bit 5
No
NR - Bit 4
No
Yes
Yes
Yes
Yes
NR - Bit 3
No
Yes
Yes
NR - Bit 2
No
Yes
Yes
NR - Bit 1
No
NR - Bit 0
No
Yes
Yes
Yes
Yes
GC - Bit 7
No
Yes
Yes
GC - Bit 6
No
Yes
Yes
GC - Bit 5
No
Yes
Yes
GC - Bit 4
No
GC - Bit 3
No
Yes
Yes
Yes
Yes
GC - Bit 2
No
Yes
Yes
GC - Bit 1
No
Yes
Yes
GC - Bit 0
No
Yes
Yes
NOTES:
1. The XRT74L73 contains mask register bits that
permit the user to alter the state of the internally
generated value for these bits.
2. The Transmit LAPD Controller/Buffer can be con-
figured to be the source of the DL bits, within the
Outbound E3 data stream.
In all, the Transmit Overhead Data Input Interface
permits the user to insert overhead data into the Out-
bound E3 frames via the following two different meth-
ods.
• Method 1 - Using the TxOHClk clock signal
• Method 2 - Using the TxInClk and the TxOHEnable
signals.
Each of these methods are described below.
6.2.2.1 Method 1 - Using the TxOHClk Clock
Signal
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