XRT74L73 Datasheet, PDF (161/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
3.4.2.1.4Parity Checking Handling of Errored Cell
Data received from the Receive UTO-
PIA Interface Block
The Receive UTOPIA Interface block will compute the
odd parity of each byte (or word) of ATM cell data it
places on the Receive UTOPIA Data bus. The Receive
UTOPIA Interface block will also output the value of
this parity bit via the RxUPrty pin. The RxUPrty pin will
contain the odd parity value of the byte or word that is
residing on the Receive UTOPIA Data bus.
The user has the option to configure the ATM Layer
processor hardware and or software to use this feature.
3.4.2.2Receive UTOPIA FIFO Manager
The RxFIFO Manager has the following
responsibilities.
• Monitoring the fill level of the RxFIFO, and alerting
the ATM Layer processor anytime the RxFIFO
contains cell data that needs to be read.
• Detecting and discarding “Runt” cells and insuring
that the RxFIFO can resume normal operation
following the removal of the “Runt” cell.
• Insuring that the RxFIFO can respond properly to
an “Overrun” condition, by generating the “RxFIFO
Overrun Condition” interrupt, discarding the result-
ing “Runt” or errored cell, and resuming proper
operation afterwards.
• Generating the “RxFIFO Underrun Condition” inter-
rupt to the local µP, when the RxFIFO has been
depleted of ATM cell data.
Receive UTOPIA FIFO Manager Features and Options
This section discusses the numerous features that
are provided by the Receive UTOPIA FIFO Manager.
Additionally, this section discusses how these fea-
tures can be optimized to suit particlar application
needs.
The Receive UTOPIA FIFO Manager provides the fol-
lowing options.
• Handshaking Mode (Octet Level vs Cell Level)
• Resetting the RxFIFO
• Monitoring the RxFIFO
3.4.2.2.1Selecting the Handshaking Mode (Octet
Level vs Cell Level)
The Receive UTOPIA Interface block offers two dif-
ferent data flow control modes for data transmission
between the ATM Layer processor and the UNI IC.
These two modes are: “Octet-Level” Handshaking
and “Cell-Level” Handshaking; as specified by the
UTOPIA Level 2, Version 8 Specifications, and are
discussed below.
3.4.2.2.1.1Octet-Level Handshaking
The UNI will be operating in the Cell-Level Handshak-
ing Mode following power up or reset. Therefore, bit 5
(Handshake Mode) within the UTOPIA Configuration
Register to must be set to “0” in order to configure the
UNI into “Octet-Level” Handshake Mode. The main sig-
nal that is responsible for data-flow control between the
ATM Layer processor and the Receive UTOPIA Inter-
face block is the RxUClav output pin.
When the UNI is operating in the Octet-Level Hand-
shake mode, the Receive UTOPIA Interface block will
assert the RxUClav output pin, when the RxFIFO
contains at least one “read cycle’s” worth of ATM Cell
Data. In other words, if the UTOPIA Data bus width is
configured to be 16 bits wide, then the RxUClav sig-
nal will be asserted when the RxFIFO contains at
least two bytes of cell data. Likewise, if the UTOPIA
Data bus width is configured to be 8 bits wide, then
the RxUClav signal will be asserted when the RxFIFO
contains at least one byte of ATM cell data. The
Receive UTOPIA Interface block will negate RxUClav
when the RxFIFO has been depleted of any data.
Therefore, the RxUClav pin exhibits a role that is similar
to a “Ready Ready” indicator in RS-232 based data
transmission systems.
The ATM Layer processor is expected to monitor the
state of the RxUClav pin very closely (either in a tight-
ly polled or interrupt driven approach). The ATM Lay-
er processor is also expected to respond very quickly
to the assertion of RxUClav and read out the cell data
in order to avoid an “Overrun Condition” in the
RxFIFO. Finally, the ATM Layer processor is expect-
ed to do one of two things, whenever RxUClav tog-
gles “low”.
1. Quickly halting its reading of data from the Receive
UTOPIA data bus.
2. Or, “validate” each byte or word of ATM cell data that
it reads from the Receive UTOPIA Data bus, by
checking the level of the RxUClav signal. In this case,
the ATM Layer processor must have the ability to
internally remove any ATM cell data bytes or words
that have been read in, after RxUClav has toggled
“low”.
Figure 37 presents a timing diagram illustrating the behav-
ior of the RxUClav pin during reads from the Receive UTO-
PIA Interface block, while operating in the Octet-Level
Handshaking Mode.
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