XRT74L73 Datasheet, PDF (106/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
Upon power up or reset, the “HEC Byte Calculator
and Insertion” feature is enabled. A “0” must be writ-
ten to this bit in order to disable this operation.
TxCP Control Register (Address = 60h)
BIT 7
BIT 6
BIT 5
Scrambler En Coset Enable
HEC Insert
Enable
R/W
R/W
R/W
1
1
1
BIT 4
TDPChk
Pattern
R/W
1
2.2.2.1.2Configuring the “HEC Byte Calculator and
Insertion” Feature for Idle Cells
The “HEC Byte Calculation and Insertion” feature can
be separately enabled or disabled for the outbound Idle
Cells. This option is exercised by writing the appropri-
ate value to bit 1 (Idle Cell HEC CalEn) within the Tx-
CP Control Register, as depicted below.
BIT 3
GFC Insert
Enable
R/W
0
BIT 2
BIT 1
BIT 0
TDPErr Inter-
rupt Enable
Idle Cell HEC
CalEn
TDPErr Inter-
rupt
Status
R/W
R/W
RUR
0
x
0
This “Read/Write” bit-field is used for enabling or dis-
abling the “Calculation and Insertion” of the HEC byte
into the Idle Cell as illustrated below. If disabling this
feature is chosen, then the 5th octet of the Idle Cells
will be transmitted to the Transmit PLCP (or Transmit
DS3 Framer) block as programmed in the “TxCP Idle
Cell Pattern Header—Byte 5” register (Address =
68h).
TABLE 9: THE RELATIONSHIP BETWEEN THE CONTENTS WITHIN BIT 1 (IC HEC CALC EN) OF THE “TXCP
CONTROL REGISTER” AND THE RESULTING HANDLING OF IDLE CELLS, BY THE “HEC BYTE
CALCULATOR”
IC HEC CALC EN
0
1
RESULT
The entire programmed Idle Cell header is transmitted without Modification
The HEC byte is calculated, via the first four bytes of the header, and is inserted into the fifth octet position
within each Idle Cell.
Upon power up or reset, the Transmit Cell Processor
will be configured such that the HEC bytes will be cal-
culated and inserted into the fifth octet position of
each Idle Cell. A “0” must be written to this bit-field in
order to disable this feature.
2.2.2.1.3Modulo-2 Addition of Coset Polynomial
to the HEC Byte Value
When enabled, the HEC Byte Calculator takes the
first four bytes of each cell and computes a CRC-8
value via the generating polynomial x⁸ + x² + x + 1.
The BISDN Physical Layer specifications (ITU
Recommendations I.432) specifies that this CRC-8 (or
HEC) value can optionally be modulo-2 added to the
polynomial x⁶ + x⁴ + x² + 1; and inserting the result of
this calculation into the fifth byte of each cell. The pur-
pose of this option is to provide protection against bit
slips. This protection is not required in transmission
systems that ensure adequate one’s density. Howev-
er, this operation does provide protection against all ze-
ros cells that could be passed to the ATM Layer during
a loss of signal condition on the transmission medium.
The ATM Forum UNI specifications also requires this
operation.
This modulo-2 addition can be enabled or disabled by
writing the appropriate value to bit 6 (Coset Enable)
within the “TxCP Control” Register, as depicted be-
low.
TxCP Control Register (Address = 60h)
BIT 7
BIT 6
BIT 5
Scrambler En Coset Enable
HEC Insert
Enable
BIT 4
TDPChk
Pattern
BIT 3
GFC Insert
Enable
BIT 2
TDPErr Inter-
rupt Enable
BIT 1
Idle Cell
HEC CalEn
BIT 0
TDPErr Inter-
rupt
Status
107