XRT74L73 Datasheet, PDF (93/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
FIGURE 8. FLOW CHART DEPICTING THE APPROACH THAT THE ATM LAYER PROCESSOR SHOULD TAKE WHEN
WRITING ATM CELL DATA INTO THE TRANSMIT UTOPIA INTERFACE BLOCK, WHEN THE UNI IS OPERATING IN
THE SINGLE PHY MODE.
START
Check the level of the TxClav pin.
Is
No
TxClav
“High”?
Yes
Is this
the first byte
Yes
(word) of a new
cell?
No
WRITING THE FIRST BYTE/WORD OF
A CELL
Perform the following, concurrently
Assert the TxSoC input pin
Place the first byte (word) on the
Transmit Utopia Data Bus.
Place the odd-parity value of this byte
(word) on the TxPrty input pin
Assert the “Transmit Utopia Data Bus
Write Enable” pin, TxEnb*.
WRITING THE REMAINING BYTES/
WORDS OF A CELL
Perform the following, concurrently
Place the first byte (word) on the
Transmit Utopia Data Bus.
Place the odd-parity value of this byte
(word) on the TxPrty input pin
Assert the “Transmit Utopia Data Bus
Write Enable” pin, TxEnb*.
Is there
any more Cells
to write
?
Yes
No
END
No
Is the
current Cell
Yes
Complete?
94