XRT74L73 Datasheet, PDF (44/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
AC17
NAME
RxTSX/RxPSOF
AE25
RxPDVAL
H23 RxOHEnable_0/
RxHDLCDat_5_0
F23 ^{RxOHEnable_1/}
RxHDLCDat_5_1
C24 ^{RxOHEnable_2/}
RxHDLCDat_5_2
AD24
RxPERR
W23
RxUClkO/
RxPClkO
TYPE
O
O
O
O
O
DESCRIPTION
Receive - Start of Transfer/Receive - Start of PPP Packet (in Chunk Mode):
The exact function of this output pin depends upon whether the XRT74L73
device has been configured to operate in the Packet Mode or Cell-Chunk Mode.
Packet Mode - RxTSX
The XRT74L73 device pulses this output pin "high" when an inband port
address is present on the "RxPData[7:0]" bus.When this output pin is "high", the
value of "RxPData[7:0]" is the address value of the "RxFIFO" to be selected.
Subsequent read operations, from "RxPData[15:0]" will be from the RxFIFO cor-
responding to this "inband" address.
Chunk Mode - RxPSOF
The XRT74L73 device pulses this output pin "high" in order to indicate that the
first byte (or word) of a given Packet is placed on the "RxPData[15:0]" pins.
NOTE: This output pin is only active if the XRT74L73 device has been config-
ured to operate in the PPP Mode.
Receive POS-PHY Interface Signal Valid Indicator:
This output signal indicates whether or not the Receive POS-PHY Interface sig-
nals (e.g., PRData[15:0], RxPSOP, RxPEOP, RxPPrty, RxPERR) are valid.This
output pin will be driven "high", when these signals are valid. Conversely, this
output pin will be driven "low" when these signals are NOT valid.
NOTE: This output pin is only active if the XRT74L73 device has been config-
ured to operate in the PPP Mode.
Receive Overhead Data Output Interface - Enable Output/Receive HDLC
Controller Data Bus - Bit 5 output:
The exact function of this output pin depends upon whether the channel has
been configured to operate in the "Clear-Channel Framer" Mode or in the "High-
Speed HDLC Controller" Mode.
Clear-Channel Framer Mode - RxOHEnable_n:
The channel will assert this output signal for one "RxOHClk_n" period when it is
safe for the local terminal equipment to sample the data on the "RxOH_n" output
pin.
High-Speed HDLC Controller Mode - RxHDLCDat_5_n:
This output pin, along with RxHDLCDat_[4:0]_n, RxHDLCDat_6_n and
RxHDLCDat_7_n function as the Receive HDLC Controller byte wide output
data bus. The Receive HDLC Controller will output the contents of all HDLC
frames via this output data bus, upon the rising edge of the "RxHDLCClk_n" out-
put signal. Hence, the user’s local terminal equipment should be designed/con-
figured to sample this data upon the falling edge of the "RxHDLCClk_n" output
clock signal.
Receive POS-PHY Interface - Error Indicator:
This output pin indicates whether or not the Receive POS-PHY Interface has
detected an error in the inbound PPP Packet.This output pin toggles "high" if the
Receive Section of the XRT74L73 device detects an FCS Error, an ABORT
sequence, or a Runt Packet.
NOTE: This output pin is only valid if the XRT74L73 device has been configured
to operate in the PPP Mode.
Receive UTOPIA Interface Clock/Receive POS-PHY Interface Clock Output:
This output pin is derived from an internal PLL.
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