XRT74L73 Datasheet, PDF (126/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
FIGURE 22. FUNCTIONAL BLOCK DIAGRAM OF RECEIVER FRAMER
ExtLOS
LOS Interrupt
AIS Interrupt
Idle Interrupt
RxAIS
RxLOS
RxIdle
RxNBData
Line Detector
RxInFrame
RxFrame
RxOHFrame
RxOHClk
Over Head
Processor
Interrupt from OH
Processor
RxOHFrame
RxOHClk
RxOH
RxFEBE (To Tx
Framer)
RxFrame
RxPOS
RxNEG
RxLineClk
LCV Error
(to PMON)
RxOOF
B3ZS
Decoder
Frame Synchronizer
RxNBClk
RxOFF
PayLoad
Overhead
MUX
PayLoad
Data _{Serial/Nibble}
Converter
RxNBDat[4]
RxNBClk
RxLineClk
Nibble
Counter
(Divide by 4)
Timing & Control
Packet
Counter
(Divide by 85)
SubFrame
Counter
(Divide by 4)
Frame
Counter
(Divide by 7)
Justify
Enable
Enable
RxFrame
New Frame
Alignment
Interrupt
OR
To
Gate
Int
Block
3.2Receive PLCP Processor
3.2.1Operation of the Receive PLCP Processor
The Receive PLCP Processor receives PLCP frame
data from the Receive DS3 Framer and locates the
boundaries of these incoming PLCP frames. The
Receive PLCP processor also extracts the PLCP
overhead bytes, computes and verifies the incoming
BIP-8 (B1) byte, transfers FEBE and Yellow Alarm
information to the “Near-End” Transmit PLCP
Processor, for transmittal back to the Far-End Terminal.
Finally, these PLCP frames (and their designated
boundaries) are routed to the Receive Cell Processor,
for further processing.
Note: The Receive PLCP Processor is disabled when the
UNI is operating in the “Direct Mapped ATM” mode.
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