XRT74L73 Datasheet, PDF (18/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
Rx DS3 Framer
C26
RxAIS_0/
RxNib_2_0/
RxHDLCDat_2_0
E25
RxAIS_1/
RxNib_2_1/
RxHDLCDat_2_1
G24
RxAIS_2/
RxNib_2_2/
RxHDLCDat_2_2
B18
RxFrame_0
A18
RxFrame_1
B17
RxFrame_2
A2
RxLineClk_0
D11
RxLineClk_1
D18
RxLineClk_2
TYPE
DESCRIPTION
O
Receive AIS Pattern Indicator/Receive Nibble Output Interface - Bit 2/
Receive HDLC Controller Data Bus - Bit 2 output pin:
The exact function of this output pin depend upon whether the XRT74L73 device
has been configured to operate in the Clear-Channel Framer/Nibble-Parallel
Interface Mode, the High-Speed HDLC Controller Mode, or in the other modes.
Other Modes - RxAIS_n:
This output pin is driven "high" whenever the Receive Section of the channel has
detected and is currently declaring an "AIS" (Alarm Indicator Signal) condition.
Clear-Channel Framer/Nibble-Parallel Interface Mode - RxNib_2_n:
If the user opts to operate the XRT74L73 device in the Nibble-Parallel Mode,
then this output pin will function as the bit 2 output from the "Receive Nibble-Par-
allel" output interface. The Receive Payload Data Output Interface block will out-
put this signal (along with RxNib_0_n, RxNib_1_n, and RxNib_3_n) upon the
rising edge of the RxClk_n output signal.
High-Speed HDLC Controller Mode - RxHDLCDat_2_n:
This output pin, along with RxHDLCDat_[7:3]_n and RxHDLCDat_[1:0]_n func-
tion as the Receive HDLC Controller byte wide output data bus. The Receive
HDLC Controller will output the contents of all HDLC frames via this output data
bus, upon the rising edge of the "RxHDLCClk_n" output signal. Hence, the
user’s local terminal equipment should be designed/configured to sample this
data upon the falling edge of the "RxHDLCClk_n" output clock signal.
O Receive Boundary of DS3 or E3 Frame Output indicator:
The exact function of this output pin depends upon whether the channel is oper-
ating in the Clear-Channel Framer/Nibble-Parallel Mode or not.
Clear-Channel Framer/Nibble-Parallel Mode
The Receive Section of the channel will pulse this output pin "high" for one nib-
ble period, when the Receive Payload Data Output interface block is driving the
very first nibble of a given DS3 or E3 frame, on the "RxNib_n[2:0]" output pins.
Clear-Channel Framer/Serial Mode
The Receive Section of the channel will pulse this output pin "high" for one bit
period, when the Receive Payload Data Output interface block is driving the very
first nibble of a given DS3 or E3 frame, on the "RxSer_n" output pin.
All Other Modes:
The Receive Section of the channel will pulse this output pin "high" when the
Receive DS3/E3 Framer block is processing the first bit within a new DS3 or E3
frame.
I
Receive (Recovered LIU) Line Clock:
This input signal serves three purposes.
1. The Receive Section of the XRT74L73 device use it to sample and latch
the signals at the "RxPOS_n" and "RxNEG_n" input pins (into the
Receive Framer/UNI circuitry).
2. This input signal functions ass the timing reference for the Receive Sec-
tions of the XRT74L73 device.
3. The Transmit Sections can be configured to use this input signal at its tim-
ing reference.
NOTE: This signal is the recovered clock from the external DS3/E3 LIU IC, which
is derived from the incoming DS3 or E3 line signal.
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