XRT74L73 Datasheet, PDF (346/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
)
I/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
BIT 6
BIT 5
BIT 4
Disable
TxLOC
LOC
Disable
RxLOC
AMI/
ZeroSup*
BIT 3
Unipolar/
Bipolar*
R/W
RO
R/W
R/W
R/W
1
0
1
0
0
BIT 2
TxLine
Clk
Invert
R/W
0
PRELIMINARY
BIT 1
RxLine
Clk
Invert
R/W
0
BIT 0
Reframe
R/W
1
The Framer IC will respond to this command by doing
the following.
1. Asserting both the RxOOF and RxLOF output
pins.
2. Generating both the Change in OOF Status and
the Change in LOF Status interrupts to the Micro-
processor.
3. Asserting both the RxLOF and RxOOF bit-fields
within the Rx E3 Configuration & Status Register,
as depicted below.
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
RxLOF
Algo
RxLOF
RxOOF
RxLOS
RxAIS
Not Used
R/W
RO
RO
RO
RO
RO
RO
0
1
1
0
0
1
1
BIT 0
RxFERF
RO
0
5.3.2.4 Performance Monitoring of the Frame
Synchronization Section, within the Receive E3
Framer block
The user can monitor the number of FAS pattern er-
rors that have been detected by the Receive E3
Framer block. This is accomplished by periodically
reading the PMON Framing Bit/Byte Error Event
Count Registers (Address = 0x52 and 0x53). The
byte format of these registers are presented below.
5.3.2.5 The RxOOF and RxLOF output pin.
The user can roughly determine the current framing
state that the Receive E3 Framer block is operating in
by reading the logic state of the RxOOF and the Rx-
LOF output pins. Table 77 presents the relationship
between the state of the RxOOF and RxLOF output
pins, and the Framing State of the Receive E3 Fram-
er block.
TABLE 77: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE
FRAMING STATE OF THE RECEIVE E3 FRAMER BLOCK
RXLOF
0
0
1
1
RXOOF
FRAMING STATE OF THE RECEIVE E3 FRAMER BLOCK
0
In Frame
1
OOF Condition (The Receive E3 Framer block is operating in the 3ms OOF period).
0
Invalid
1
LOF Condition
5.3.2.6 E3 Receive Alarms
5.3.2.7 The Loss of Signal (LOS) Alarm
Declaring an LOS Condition
The Receive E3 Framer block will declare a Loss of
Signal (LOS) Condition, when it detects 32 consecu-
tive incoming “0’s” via the RxPOS and RxNEG input
pins or if the ExtLOS input pin (from the XRT7300
DS3/E3/STS-1 LIU IC) is asserted. The Receive E3
Framer block will indicate that it is declaring an LOS
condition by.
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