XRT74L73 Datasheet, PDF (143/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
The “Detection” State
When the “HEC Byte Error Detection/Correction”
algorithm is operating in the Detection mode, then
all errored cells (e.g., those cells with single-bit errors
and multi-bit errors) will be discarded, unless config-
ured otherwise. To configure the Receive Cell Pro-
cessor to retain errored cells, write to bit 0 (HEC Error
Ignore) of the RxCP Configuration register (Address
= 4Ch), as described above.
The “HEC Byte Error Correction/Detection” Algorithm
will transition back into the “Correction” state once the
Receive Cell Processor has detected “M” consecutive
cells with the correct HEC byte values. The user has
the option to use the following values for “M”: 0, 1, 3,
and 7. To configure the UNI to use any of these val-
ues for M, write the appropriate values to the “RxCP
Additional Configuration” Register (Address = 4Dh),
as depicted below.
RxCP Additional Configuration Register (Address = 4Dh)
BIT 7
BIT 6
Unused
RO
RO
BIT 5
User Cell Filter
Discard
R/W
BIT 4
User Cell Filter
Enable
R/W
BIT 3
BIT 2
Correction Threshold [1, 0]
R/W
R/W
BIT 1
Correct Enable
R/W
BIT 0
Unused
RO
The definition of the bits relevant to the “HEC Byte Er- out of the “Correction” as dictated by the “Correction
ror Correction/Detection” algorithm follow:
Threshold”.
Bit 1—Correction (Mode) Enable
This “Read/Write” bit field is used to enable/disable
the “Correction Mode” portion of the “HEC Byte Error
Correction/Detection” algorithm. If a “0” is written to
this bit-field, the “HEC Byte Error Correction/Detection”
algorithm will be disabled from entry/operation in the
“Correction” mode. Therefore, the Receive Cell Pro-
cessor will only operate in the “Detection” mode. If a
“1” is written to this bit field then the “HEC Byte Error
Correction/Detection” algorithm will transition into and
Bits 2 and 3—Correction Threshold [1, 0]
These “Read/Write” bit-fields are used to select the
“Correction” Threshold for the “HEC Byte Error Cor-
rection/Detection” algorithm. The following table re-
lates the content of these bit-fields to the Correction
Threshold Value (M). Once again, M is the number of
consecutive “Error-Free” cells that the Receive Cell
Processor must detect before the “HEC Byte Correc-
tion/Detection” algorithm will allow a transition back
into the “Correction” Mode.
TABLE 24: THE RELATIONSHIP BETWEEN CORRTHRESHOLD[1:0] AND THE “CORRECTION THRESHOLD” VALUE (M)
BIT 3
0
0
1
1
BIT 2
0
1
0
1
CORRECTION THRESHOLD VALUE (M)
M=0
M=1
M=3
M=7
3.3.2.3Cell Filtering
As mentioned earlier, the Receive Cell Processor will fil-
ter (e.g., discard) incoming cells based upon the follow-
ing criteria.
• HEC Byte Errors (via the “HEC Byte Correction/
Detection” algorithm, as described in 7.3.2.2.)
• Idle Cells
• Header Byte Patterns—User Cells
• Segment OAM Cells
Each of these cell filtering approaches are presented
below.
Filtering of Cells with HEC Byte Errors
Please see the “HEC Byte Correction/Detection”
algorithm in Section 7.3.2.2.
3.3.2.3.1Idle Cell Filtering
The Receive Cell Processor can be configured to ei-
ther discard or retain Idle cells by writing to bit 4 (Idle
Cell Discard) of the RxCP Configuration Register, as
depicted below.
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