XRT74L73 Datasheet, PDF (107/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TxCP Control Register (Address = 60h)
BIT 7
R/W
BIT 6
R/W
BIT 5
R/W
BIT 4
R/W
BIT 3
R/W
BIT 2
R/W
BIT 1
R/W
BIT 0
RUR
A “1” in this bit-field will enable this modulo addition.
Conversely, a “0” in this bit-field will disable this
operation.
Upon power up or reset, the Transmit Cell Processor
will be configured such that the coset polynomial is
modulo-2 added to the HEC byte prior to insertion in-
to the cell. A “0” must be written to this bit to disable
this operation.
2.2.2.1.4Inserting Errors into the HEC Byte
via Software Control
The XRT74L73 DS3/E3 UNI allows the user to insert
errors into the HEC bytes of “outbound” cells in order
to support equipment testing. One such test that the
user may wish to verify is that the HEC byte verifica-
tion (e.g., error detection and/or correction) features
of some “Far-End” terminal equipment is functioning
properly. The user would conduct this test by trans-
mitting cells with erroneous HEC byte values to the
“unit under test” (UUT). This option can be exercised
by writing the appropriate data into the TxCP Error
Mask register, which is located at address 62h within
the UNI.
TxCP Error Mask Register; (Address = 62h)
BIT 7
R/W
BIT 6
R/W
BIT 5
R/W
BIT 4
BIT 3
HEC Error Mask Byte
R/W
R/W
BIT 2
R/W
BIT 1
R/W
BIT 0
R/W
The Transmit Cell Processor automatically XORs the
HEC Byte (or each “outbound” cell) with the contents
of this register. The result of this operation is written
back into the fifth octet position of each of these cells.
To prevent injecting errors into the HEC byte, the con-
tents of this register must be set to 00h, the default
value.
2.2.2.2The Cell Scrambler
The Cell Scrambler takes bytes 6 through 53 of each
cell (the payload) and scrambles the contents of these
bytes. The purpose of scrambling the cell payload
bytes is to reduce the possibility of the contents of the
cell payload mimicking patterns that are used for
framing and cell delineation purposes. The scrambler
generating polynomial is x⁴³ + 1. The Cell Scrambler
can be enabled or disabled by setting or clearing bit 7
(Scrambler Enable) within the “TxCP Control” Register,
as depicted below.
TxCP Control Register (Address = 60h)
BIT 7
Scrambler
Enable
R/W
x
BIT 6
BIT 5
Coset Enable
HEC Insert
Enable
R/W
R/W
1
1
BIT 4
TDPChk
Pattern
R/W
1
BIT 3
GFC Insert
Enable
R/W
0
BIT 2
TDPErr Inter-
rupt Enable
R/W
0
BIT 1
Idle Cell
HEC CalEn
R/W
1
BIT 0
TDPErr Inter-
rupt
Status
RUR
0
A “1” in this bit-field enables the Cell Scrambler. Con-
versely, a “0” in this bit-field disables the Cell-Scrambler.
Upon power up or reset, the Cell Scrambler function
will be enabled. Therefore, a “0” must be written to
this bit in order to disable cell scrambling.
2.2.2.3GFC Nibble-Field Serial Input Port
The first four bits in the first header byte of each cell
are allocated for carrying “Generic Flow Control” (GFC)
information. The user can externally insert their own
values for the GFC nibble-field into each outbound
cell, via a serial input port. This serial input port (the
“Transmit GFC-Nibble-field” Serial Input port) will be
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