XRT74L73 Datasheet, PDF (165/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
RxFIFO Empty
RXFIFO EMPTY (BIT 0)
0
1
MEANING
RxFIFO is not empty
RxFIFO is empty.
3.4.2.2.2UTOPIA Modes of Operation (Single PHY
and Multi-PHY operation)
The UNI chip can support both Single-PHY and Multi-
PHY operation. Each of these operating modes are
discussed below.
3.4.2.2.3Single PHY Operation
The UNI chip will be operating in the Multi-PHY mode
upon power up or reset. Therefore, a “1” must be writ-
ten into Bit 4 of the UTOPIA Configuration Register as
depicted below in order to configure the UNI into the sin-
gle-PHY Mode.
UTOPIA Configuration Register: Address = 6Ah
BIT 7
BIT 6
Unused
RO
xx
BIT 5
Handshake Mode
R/W
x
BIT 4
M-PHY*/S-PHY
R/W
1
BIT 3
CellOf52
Bytes
R/W
x
BIT 2
BIT 1
TFIFODepth [1, 0]
R/W
xx
BIT 0
UtWidth16
R/W
x
Writing a “1” to this bit-field configures the UNI to oper-
ate in the Single-PHY mode. Writing a “0” configures
the UNI to operate in the Multi-PHY mode.
In Single-PHY operation, the ATM layer processor is
pumping data into and receiving data from only one
UNI device, as depicted in Figure 39 . ATM Cell data
is read from the RxFIFO, via the Receive UTOPIA
Data Bus, provided that the Receive UTOPIA Output
enable signal (RxUEn) is low. The data on the Receive
UTOPIA Data bus is updated on the rising edge of
the Receive UTOPIA clock (RxUClk). The Receive
UTOPIA Interface block will pulse the Receive start of
cell signal (RxUSoC) when the first byte (or word) of a
new cell is present on the Receive UTOPIA Data bus.
Odd parity of the output byte or word is calculated and
output at RxUPrty pin.
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