XRT74L73 Datasheet, PDF (85/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
Example-1
For example, if the Transmit UTOPIA Interface block
is configured to process 53 bytes per cell, then follow-
ing the assertion of the TxUSoC pin (which is coinci-
dent with the placement of the first byte of the cell on
the Transmit UTOPIA Data bus), the Transmit UTOPIA
Interface block will read in and process 52 more bytes
of data via the Transmit UTOPIA data bus resulting in
a total of 53 bytes being processed. After the Trans-
mit UTOPIA Interface block has read in the 53rd byte,
it will no longer read in any more data from the ATM
Layer Processor, until the TxUSoC pin has been as-
serted.
Example-2
If the ATM Layer processor were to prematurely as-
serts the TxUSoC pin, (e.g., when the 52nd byte is
present on the Transmit UTOPIA data bus, then the
Transmit UTOPIA Interface block will interpret the
previous 52 bytes of cell data as a “runt” cell. The
Transmit UTOPIA Interface block will then generate a
“Change of Cell Alignment” interrupt and will proceed
to discard this runt cell.
TxUClav/TFullB*—TxFIFO Cell Available/TxFIFO
Full*
This output signal is used to provide some data flow
control between the ATM Layer processor and the
Transmit UTOPIA Interface block. Please See Section
1.1.2.2.1 for more information regarding this signal.
Selecting the UTOPIA Data Bus Width
The UTOPIA data bus width can be selected to be ei-
ther 8 or 16 bits by writing the appropriate data to the
UTOPIA Configuration Register, as shown below.
UTOPIA Configuration Register: Address = 6Ah
BIT 7
BIT 6
Unused
RO
BIT 5
Handshake Mode
R/W
BIT 4
M-PHY
R/W
BIT 3
CellOf52 Bytes
R/W
BIT 2
BIT 1
TFIFODepth[1, 0]
R/W
BIT 0
UtWidth16
R/W
If a UTOPIA Data Bus width of 8 bits is chosen, then
only the Transmit UTOPIA Data inputs: TxUData[7:0]
will be active. (The input pins: TxData[15:8] will not be
active). If a UTOPIA Data bus width of 16 bits is cho-
sen, then all of the Transmit UTOPIA Data inputs: Tx-
Data[15:0] will be active. The following table relates
the value of Bit 0 (UtWidth) within the UTOPIA Con-
figuration Register, to the corresponding width of the
UTOPIA Data bus.
TABLE 3: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT FIELD 0 (UTWIDTH16) WITHIN THE UTOPIA
CONFIGURATION REGISTER AND THE OPERATING WIDTH OF THE UTOPIA DATA BUS
VALUE FOR UTWIDTH16
0
1
WIDTH OF UTOPIA DATA BUS
8 bit wide Data Bus
16 bit wide Data Bus
Note:
1. The selection of this bit also affects the width of the
Receive UTOPIA Data bus.
2. Upon power up or reset, the UTOPIA Data Bus width
will be 8 bits. Therefore, a “1” must be written to this bit
in order to set the width of the Transmit UTOPIA (and the
Receive UTOPIA) to 16 bits.
2.1.2.1.2Selecting the Cell Size (Number of Octets
per Cell)
The UNI can be configured to select the number of oc-
tets per cell that the Transmit UTOPIA Interface block
will process, following each assertion of the TxUSoC
input pin. Specifically, the following cell size options
are available.
• If the UTOPIA Data Bus width is set to 8 bits then
the user can choose:
– 52 bytes (with no HEC byte in the cell), or
– 53 bytes (with either a dummy or actual HEC byte
in the cell)
• If the UTOPIA Data Bus width is set to 16 bits then
the user can choose:
– 52 bytes (with no HEC byte in the cell), or
– 54 bytes (with either a dummy or actual HEC byte,
and a stuff byte in the cell)
The selection is made by writing the appropriate data to bit
3 (CellOf52 Bytes) within the UTOPIA Configuration
86