XRT74L73 Datasheet, PDF (92/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
FIGURE 7. SIMPLE ILLUSTRATION OF SINGLE-PHY OPERATION
To/From
DS3 LIU
DS3 UNI
TxPOS _{RxUData[15:0]}
TxNEG
RxUClav
TxLineClk
RxUSoC
RxUEn
RxPOS
RxUPrty
RxNEG
RxUClk
RxLineClk
TxUData[15:0]
TxUClav
TxUSoC
TxUEn
TxUPrty
TxUClk
ATM Switch
Rx ATM Cell Data
Rx Flow Control Input
Rx Start of Cell Input
Rx Read Output Enable Signal
Rx Utopia Data Bus Parity
Rx FIFO Clock Signal
Tx ATM Cell Data
Flow Control Input
Start of Cell Output
Tx Write Enable Output
Tx Utopia Data Bus Parity
Tx FIFO Clock Signal
(ATM Layer Device)
This section presents a detailed description of the
Transmit UTOPIA Interface block operating in the
“Single-PHY” mode. A description of the Receive
UTOPIA Interface block operating in the “Single-PHY”
mode is presented in Section 7.4.2.2.2.1. Whenever
the ATM Layer Processor wishes to write one or a se-
ries of ATM cells to the Transmit UTOPIA Interface
block, it must do the following.
1. Check the level of the TxUClav output pin.
If the TxUClav pin is “high” then there is available
space in the TxFIFO for more ATM cell data and the
ATM Layer Processor may begin writing cell data to
the Transmit UTOPIA Interface block. However, if the
TxUClav pin is “low”, then the TxFIFO is too full to ac-
cept anymore data and the ATM Layer Processor
must wait until TxUClav toggles “high” before writing
any cell data to the Transmit UTOPIA Interface block.
Note: The actual meaning of TxUClav toggling “low”
depends upon whether the UNI is operating in the “Cell
Level” or “Octet Level” handshake modes.
2. Apply the first byte (or word) of the new cell to the
Transmit UTOPIA Data Bus.
The ATM Layer processor must designate this byte
(or word) as the beginning of a new cell, by pulsing
the TxUSoC pin “high” for one clock period of TxUClk.
3. Apply the Odd-Parity value of this first byte (or word),
currently residing on the Transmit UTOPIA Data Bus,
to the TxUPrty input pin.
This should be done concurrently with pulsing the Tx-
USoC input pin “high”.
4. Assert the “Transmit UTOPIA Data Bus”—Write
Enable Signal, TxUEn.
This step should also be done concurrently with pulsing
the TxUSoC input pin “high”.
When writing the subsequent bytes (word) of the cell,
the ATM Layer Processor must repeatedly exercise
Steps 3 and 4, of the above list.
If the UNI is operating in the Octet-Level handshake
mode, then the ATM Layer processor should check
the level of the TxUClav signal, at least once for ev-
ery four (4) writes of ATM cell data to the Transmit UTO-
PIA Interface block.
If the UNI is operating in the Cell-Level Handshake
mode, then the ATM Layer Processor should check
the level of the TxUClav signal, as it nears completion
of writing in a given cell.
The above-mentioned procedure is also depicted in
Flow-Chart Form in Figure 8 ; and in Timing Diagram
form in Figure 9 and 10.
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