XRT74L73 Datasheet, PDF (229/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
NOTE: The user will typically make the selection based
upon the set-up and hold time requirements of the Transmit
LIU IC.
FIGURE 77. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG
ARE CONFIGURED TO BE UPDATED ON THE RISING EDGE OF TXLINECLK
t32
TxLineClk
t30
t33
TxPOS
TxNEG
FIGURE 78. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG
ARE CONFIGURED TO BE UPDATED ON THE FALLING EDGE OF TXLINECLK
t32
TxLineClk
t31
t33
TxPOS
TxNEG
4.2.6 Transmit Section Interrupt Processing
The Transmit Section of the XRT74L73 can generate
an interrupt to the Microcontroller/Microprocessor for
the following two reasons.
• Completion of Transmission of FEAC Message
• Completion of Transmission of LAPD Message
4.2.6.1 Enabling Transmit Section Interrupts
The Interrupt Structure, within the XRT74L73 con-
tains two hierarchical levels:
• Block Level
• Source Level
The Block Level
The Enable State of the Block Level for the Transmit
Section Interrupts dictates whether or not interrupts
(if enabled at the source level), are actually enabled.
These Transmit Section interrupts can be enabled or
disabled at the Block Level, by writing the appropriate
data into Bit 1 (Tx DS3/E3 Interrupt Enable) within the
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