XRT74L73 Datasheet, PDF (20/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
PIN DESCRIPTION
PIN#
B23
A23
C22
NAME
RxOHClk_0/
RxHDLCClk_0
RxOHClk_1/
RxHDLCClk_1
RxOHClk_2/
RxHDLCClk_2
D21 RxOHFrame_0/
RxHDLCDat_4_0
C20 ^RxOHFrame_1/
RxHDLCDat_4_1
B20 ^RxOHFrame_2/
RxHDLCDat_4_2
TYPE
O
O
DESCRIPTION
Receive Overhead Data Output Interface-Clock/Receive HDLC Controller -
Clock output:
The exact function of this output pin depends upon whether the channel has
been configured to operate in the "Clear-Channel Framer" mode or in the "High-
Speed HDLC Controller" Mode.
Clear-Channel Framer Mode - RxOHClk_n:
The channel will output the overhead bits (within the incoming DS3 or E3
frames) via the RxOH_n output pin, upon the falling edge of this clock signal.As
a consequence, the user’s local terminal equipment should use the rising edge
of this clock signal to sample the data on both the "RxOH" and "RxOHFrame"
output pins.
NOTE: This clock signal is always active.
High-Speed HDLC Controller Mode - RxHDLCClk_n:
This output pin functions as the "Receive HDLC Controller" Data bus clock out-
put. The Receive HDLC Controller block outputs the contents of all received
HDLC frames via the "Receive HDLC Controller Data bus (RxHDLCDat_[7:0]_n)
upon the rising edge of this clock signal. Hence, the user’s local terminal equip-
ment should be designed/configured to sample this data upon the falling edge of
this clock signal.
Receive Overhead Data Interface - Framing Pulse indicator/Receive HDLC
Controller Data Bus - Bit 4 output:
The exact function of this output pins depends upon whether the channel has
been configured to operate in the "Clear-Channel Framer" Mode or in the "High-
Speed HDLC Controller" Mode.
Clear-Channel Framer Mode - RxOHFrame_n:
This output pin pulses "high" whenever the Receive Overhead Data Output Inter-
face block outputs the first overhead bit of a new DS3 or E3 frame.
High-Speed HDLC Controller Mode - RxHDLCDat_4_n:
This output pin, along with RxHDLCDat_[3:0]_n and RxHDLCDat_[7:5]_n func-
tion as the Receive HDLC Controller byte wide output data bus. The Receive
HDLC Controller will output the contents of all HDLC frames via this output data
bus, upon the rising edge of the "RxHDLCClk_n" output signal. Hence, the
user’s local terminal equipment should be designed/configured to sample this
data upon the falling edge of the "RxHDLCClk_n" output clock signal.
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