XRT74L73 Datasheet, PDF (37/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
PIN DESCRIPTION
PIN#
NAME
AF16
AE16
AD16
AF15
AE15
AD15
AC14
AF14
AD14
AF13
AE13
AD13
AC12
AF12
AE12
AD12
TxUData0/
TxPData0
TxUData1/
TxPData1
TxUData2/
TxPData2
TxUData3/
TxPData3
TxUData4/
TxPData4
TxUData5/
TxPData5
TxUData6/
TxPData6
TxUData7/
TxPData7
TxUData8/
TxPData8
TxUData9/
TxPData9
TxUData10/
TxPData10
TxUData11/
TxPData11
TxUData12/
TxPData12
TxUData13/
TxPData13
TxUData14/
TxPData14
TxUData15/
TxPData15
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
TYPE
I
DESCRIPTION
Transmit UTOPIA Data Bus Inputs/Transmit POS-PHY Data Bus Inputs:
The exact function of these input pins depends upon whether the XRT74L73 is
operating in the ATM UNI Mode or in the PPP Mode.
ATM UNI Operation - TxUData[15:0]
These input pins comprise the Transmit UTOPIA Data Bus input pins. When the
ATM Layer Processor wishes to transmit ATM cell data through the XRT72L73
ATM UNI, it must place this data on these pins. The data, on the Transmit UTO-
PIA Data Bus is latched into the Transmit UTOPIA Interface block upon the ris-
ing edge of TxUClk.
PPP Operation - TxPDATA[15:0]
These input pins comprise the Transmit POS-PHY Data Bus input pins. When a
Network Processor wishes to transmit PPP data through the XRT74L73 Framer/
UNI IC, it must place this data on these pins. The data, on the Transmit POS-
PHY Data Bus is latched into the Transmit POS-PHY Interface block upon the
rising edge of TxPClk.
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