XRT74L73 Datasheet, PDF (160/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
TABLE 28: THE RELATIONSHIP BETWEEN THE CONTENTS WITHIN BIT 0 (UTWIDTH16) WITHIN THE UTOPIA
CONFIGURATION REGISTER, AND THE OPERATING WIDTH OF THE UTOPIA DATA BUS
VALUE FOR UTWIDTH16
0
1
WIDTH OF UTOPIA DATA BUS
8 bit wide Data Bus
16 bit wide Data Bus
Note:
1. The selection of this bit also affects the width of the
Transmit UTOPIA Data bus.
2. The UTOPIA Data Bus width will be 8 bits, upon power
up or reset. Therefore, a “1” must be written to this bit
in order to set the width of the Receive UTOPIA (and the
Transmit UTOPIA data bus) to 16 bits.
3.4.2.1.3Selecting the Cell Size (Number of Octets
per Cell)
The UNI allows the user to select the number of oc-
tets per cell that the Receive UTOPIA Interface block
will process. Specifically, the following cell size op-
tions are available.
• If the UTOPIA Data Bus is 8 bits wide then the user
can choose:
– 52 bytes (with no HEC byte in the cell), or
– 53 bytes (with either a dummy or actual HEC byte
in the cell)
• If the UTOPIA Data Bus is 16 bits wide then the
user can choose:
– 52 bytes (with no HEC byte in the cell), or
– 54 bytes (with either a dummy or actual HEC byte,
and a stuff byte in the cell)
The selection is made by writing the appropriate data to
bit 3 (CellOf52Bytes) within the UTOPIA Configuration
Register, as depicted below.
UTOPIA Configuration Register: (Address = 6Ah)
BIT 7
BIT 6
Unused
RO
BIT 5
Handshake Mode
R/W
BIT 4
M-PHY
R/W
BIT 3
CellOf52 Bytes
R/W
BIT 2
BIT 1
TFIFODepth[1, 0]
R/W
BIT 0
UtWidth16
R/W
The following table specifies the relationship between
the value of this bit and the number of octets/cell that
the Receive UTOPIA Interface block will process.
TABLE 29: THE RELATIONSHIP BETWEEN THE VALUE OF BIT 3 (CELLOF52BYTES) WITHIN THE UTOPIA
CONFIGURATION REGISTER, AND THE NUMBER OF OCTETS PER CELL THAT WILL BE PROCESSED
BY THE TRANSMIT AND RECEIVE UTOPIA INTERFACE BLOCKS.
CELLOF52 BYTES
0
1
NUMBER OF BYTES/CELLS
53 bytes when the UTOPIA Data Bus width is 8 bits wide.
54 bytes when the UTOPIA Data Bus width is 16 bits wide.
52 bytes, regardless of the width of the UTOPIA Data Bus
Note: This selection applies to both the Transmit UTOPIA
and Receive UTOPIA interface blocks. Additionally, the
shaded selection reflects the default condition upon power
up or reset.
An Advisory
The user must insure that the ATM Layer processor
only reads in (from the Receive UTOPIA Interface
block) the “configured” number of octets per cell,
following the latest assertion of the RxUSoC output
pin. If the ATM Layer processor continues to try to
read-in more octets, it will end up reading in in-valid
data.
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