XRT74L73 Datasheet, PDF (212/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
register, in order to keep the Transmit FEAC Processor
enabled.
Once this step has been completed, the Transmit
FEAC Processor will proceed to transmit the 16 bit
FEAC code via the outbound DS3 frames. This 16 bit
FEAC message will be transmitted repeatedly 10
consecutive times. Hence, this process will require a
total of 160 DS3 Frames. During this process the Tx
FEAC Busy bit (Bit 0, within the Transmit DS3 FEAC
Configuration and Status register) will be asserted, in-
dicating that the Tx FEAC Processor is currently
transmitting the FEAC Message to the remote Termi-
nal. This bit-field will toggle to "0" upon completion of
the 10th transmission of the FEAC Code Message.
The Transmit FEAC Processor will generate an inter-
rupt (if enabled) to the local µP/µC, upon completion
of the 10th transmission of the FEAC Message. The
purpose of having the Framer IC generating this inter-
rupt is to let the local µP/µC know that the Transmit
FEAC Processor is now available and ready to trans-
mit a new FEAC message. Finally, once the Transmit
FEAC Processor has completed its 10th transmission
of a FEAC Code Message it will then begin sending
all 1s in the FEAC bit-field of each DS3 Frame. The
Receive FEAC Processor (at the remote terminal
equipment) will interpret this all 1s message as an
Idle FEAC Message. The Transmit FEAC Processor
will continue sending all 1s in the FEAC bit field, for
an indefinite period of time, until the local µP/µC com-
mands it to transmit a new FEAC message.
Figure 68 presents a flow chart depicting how to use
the Transmit FEAC Processor.
FIGURE 68. A FLOW CHART DEPICTING HOW TO TRANSMIT A FEAC MESSAGE VIA THE FEAC TRANSMITTER
SSTTAARRTT
11
WWRRITITEESSIXIX-B-BITIT“O“OUUTTBBOOUUNNDD””FFEEAACCVVAALLUUEE
ININTTOOTTHHEETTxDxDSS33FFEEAACCRRegeigsitsetrer
TThihsisrergegisitsetrerisislolocactaetdedatatAAddddrersesss0x03x23.2.
E_EN_NA_AB_BL_LE_ET_TH_HE_ET_TR_RA_AN_NS_SM_MIT_ITF_FE_EA_AC_CP_PR_RO_OC_CE_ES_SS_SO_OR_R. _.
TThihsisisisacaccocmomplpilsihsehdedbybywwrirtiitnigng“x“xxxxxxxx1xx1xx”x”
inintotothteheTTxxDDSS33FFEEAACCCCoonnfifgiguurartaitoionn&&SStattautus _{sRRegegisitsetrer}
ININITITIAIATTEETTRRAANNSSMMISISSSIOIONNOOFFTTHHEE“O“OUUTTBBOOUUNNDD””
FFEEAACCMMEESSSSAAGGEE. _.
TThhisisisisacaccocommpplilsihshededbbyywwrirtiitningg“x“xxxxxxxxxxx11xx””inintotoththee
TTxxDDSS33FFEEAACCCCoonnfifgiguurartaitoionn&&SStattautus _{sRRegegisitsetre.r.}
TTRRAANNSSMMITITFFEEAACCPPRROOCCEESSSSOORRPPRROOCCEEEEDDSSTTOO
ININSSEERRTTTTHHEE1166-B-BITITMMEESSSSAAGGEE(I(NINAABBITIT-B-BYY-B-BITIT
MMAANNNNEERR) _{)ININTTOOTTHHEE“F“FEEAACC””BBITIT-F-FIEIELLDDSSOOFF}
EEAACCHHOOUUTTBBOOUUNNDDDDSS33FFRRAAMMEE. _.
HHasas
NO
ththee1166-b-bitit
FFEEAACCMMesessasgageebbeeenen
trtarnansmsmitittetdedtotoththee
RRememotoeteTTeremrminianlal
1010titmimeses
??
YES
IsIs
TTrarnansmsmisissisoinon
oof _{fthtehe1166BBititFFEEAACC}
MMesessasgaege
CCoommpplelteete
??
YES
NO
GGEENNEERRAATTEETTHHEETTRRAANNSSMMITITFFEEAACC
ININTTEERRRRUUPPTT
T_TR_RA_AN_NS_SM_MIT_ITF_FE_EA_AC_CP_PR_RO_OC_CE_ES_SS_SO_OR_RE_EN_NC_CA_AP_PS_SU_UL_LA_AT_TE_ES_S
TTHHEE““OOUUTTBBOOUUNNDD””FFEEAACCVVAALLUUEEININTTOOAA1166BBITIT
FFRRAAMMININGGSSTTRRUUCCTTUURREE. _.
ININVVOOKKEETTHHEE““TTRRAANNSSMMITITFFEEAACCININTTEERRRRUUPPTT
SSEERRVVICICEERROOUUTTININEE. _.
11
NOTE: For a detailed description of the Receive FEAC Pro-
cessor (within the Receive DS3 HDLC Controller block),
please see Section 4.3.3.1.
4.2.3.2 Message-Oriented Signaling (e.g.,
LAP-D) processing via the Transmit DS3 HDLC
Controller
213