XRT74L73 Datasheet, PDF (81/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
2.0TRANSMIT SECTION
The purpose of the Transmit section of the XRT74L73
DS3/E3 ATM UNI is to allow a local ATM Layer (or
ATM Adaptation Layer) processor to transmit ATM
Cell data to a remote piece of equipment via a public
or leased DS3 transport medium.
The Transmit section of the DS3/E3 UNI chip consists
of the following blocks:
• Transmit UTOPIA Interface
• Transmit Cell Processor
• Transmit PLCP Processor
• Transmit DS3/E3 Framer
The ATM Layer processor will write ATM Cell Data to the
Transmit UTOPIA Interface Block of the UNI device. The
Transmit UTOPIA Interface block provides the industry
standard ATM/PHY interface functions. The Transmit UTO-
PIA Interface Block will ultimately write this cell data to an
internal FIFO (referred to as TxFIFO throughout this docu-
ment); where it can be read and further processed by the
Transmit Cell Processor. The Transmit UTOPIA Interface
block will also perform some parity checking on the data
that it receives from the ATM Layer processor; and will
provide signaling to support data-flow control between the
ATM Layer Processor and the Transmit UTOPIA Interface
block.
The Transmit Cell Processor block will read in the
ATM cell from the TxFIFO. It will then (optionally) pro-
ceed to take the first four octets of a given cell and
compute the HEC (Header Error Check) byte from
these bytes. Afterwards the Transmit Cell Processor
will insert this HEC byte into the 5th octet position
within the cell. The Transmit Cell Processor will also
(optionally) scramble the payload portion of the cell
(bytes 6 through 53) in order to prevent user data
from mimicking framing or control bits/bytes. Once
the cell has gone through this process it will then be
transferred to the Transmit PLCP Processor (or
Transmit DS3 Framer, if the “Direct Mapped” ATM
option is selected). If the TxFIFO (within the Transmit
UTOPIA Interface block) is depleted and has no
(user) cells available, then the Transmit Cell Processor
will automatically generate, process and transmit Idle
cells, in the exact same manner as with user cells.
This generation and transmission of Idle cells is also
known as cell-rate decoupling (e.g., Idle cells are
generated in order to fill up the bandwidth of the PMD
carrier requirements—44.736 Mbps in this case). The
Transmit Cell Processor has provisions to allow the
for the generation and transmission of an OAM cell
via software control.
Note: the OAM cells will be subjected to the same
processing as are user and Idle cells (e.g., HEC Byte
Calculation and Insertion, Cell Payload Scrambling).
The Transmit PLCP Processor block will take 12 ATM
cells and pack them into a single PLCP frame. In addi-
tion to the ATM Cells, the PLCP frame will consists of
numerous overhead bytes and either a 13 or 14 nibble
trailer to frequency justify the PLCP frame to the spec-
ified 8 kHz frame rate. Once these PLCP frames have
been formed they will be transferred to the Transmit
DS3 Framer.
The Transmit DS3 Framer will take the PLCP frame
(or ATM cells, if the Direct-Mapped ATM option was
selected), and insert this data into the payload por-
tions of the DS3 frame. The Transmit DS3 Framer will
also generate and insert overhead bits that support
framing, performance monitoring (parity bits), path
maintenance data link as well as alarm and status
information originating from the (Near-End) Receiver
section of this UNI. The purpose of these alarm and
status information bits is to alert the far-end equipment
that the (Near End) UNI Receiver has detected some
problems in receiving data from it. The Transmit DS3
Framer supports both the C-bit Parity and M13 Framing
Formats.
The following sections discuss the blocks comprising
the Transmitter Portion of the DS3/E3 UNI in detail.
2.1Transmit UTOPIA Interface Block
2.1.1Brief Description of the Transmit UTOPIA
Interface
The Transmit UTOPIA Interface Block provides a
“UTOPIA Level 2” compliant interface that allows the
ATM Layer or ATM Adaptation Layer processors to in-
terconnect to the UNI device. The ATM Layer
processor will write ATM cell data into the UNI via
the Transmit UTOPIA Interface block. The Transmit
UTOPIA Interface block is capable or receiving ATM
cell data at data rates of up to 800 Mbps. This inter-
face will support both an 8 and 16 bit wide data bus.
Since the ATM Layer processor writes ATM cell data
into the Transmit UTOPIA Interface block at clock
rates independent of the line bit rate (in this case, DS3),
the received data (from the ATM layer processor) is
written into an internal FIFO. This FIFO will be re-
ferred to as the TxFIFO throughout this document.
The contents of the TxFIFO will be read-in and further
processed by the Transmit Cell Processor. Data-flow
control between the ATM Layer processor and the
Transmit UTOPIA Interface block is provided by the
TxUClav pin, Figure 3 presents a simple illustration of
the Transmit UTOPIA interface block and the associ-
ated pins.
82