English
Language : 

XRT74L73 Datasheet, PDF (129/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
The State Machine diagram of the Receive PLCP
Processor framing algorithm is presented in Figure 25
, and each of these framing modes are discussed.
FIGURE 25. STATE MACHINE DIAGRAM OF THE RECEIVE PLCP PROCESSOR FRAMING ALGORITHM
Un-Framed
Mode
2 Consecutive sets of A1, A2, and POI
bytes are correct, and the recovered POIs
are in the correct sequence.
The OOF
condition
persists for
more than
1ms.
Errors are detected in two
consecutive framing bytes
(A1, A2) or 2 consecutive
POIs are incorrect.
In-Frame
Mode
Out-of-Frame
Mode
2 Consecutive sets of A1, A2, and POI
bytes are correct, and the recovered POIs
are in the correct sequence.
3.2.2.1.1The Un-Framed Mode
When the Receive PLCP processor is operating in
the “Un-Framed” mode, it does not have any form of
frame synchronization with the incoming PLCP data.
The Receive PLCP Processor will indicate that it is in
the “Un-Framed” Mode to external circuitry by assert-
ing both the RxPOOF and RxPLOF output pins and
the “POOF Status” and “PLOF Status” bits within the
RxPLCP Configuration/Status Register, as depicted
below.
RxPLCP Configuration/Status Register (Address = 44h)
BIT 7
x
BIT 6
BIT 5
Unused
x
x
BIT 4
x
BIT 3
Reframe
x
BIT 2
POOF Status
1
BIT 1
PLOF Status
1
BIT 0
Yellow Status
x
The Receive PLCP Processor will attempt to acquire
PLCP framing once the Receive DS3 Framer has
reached the “In-Frame” state. Specifically, the
Receive PLCP Processor will attempt to find the
boundaries of the PLCP frames by first searching for
the Frame Alignment bytes: A1 and A2. The value of
the A1 and A2 bytes are F6h and 28h, respectively.
After the Receive PLCP Processor locates the Frame
Alignment bytes, it will then begin to read and align
itself in accordance with the POI (Path Overhead
Indicator) bytes.
The Receive PLCP processor will declare itself “in-
frame” if two consecutive sets of A1, A2 and POI bytes
are correct and if the received POIs are in the correct
sequence.
130