XRT74L73 Datasheet, PDF (35/488 Pages) Exar Corporation – 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PIN DESCRIPTION
PIN#
NAME
Tx UTOPIA Interface
AC11
AF11
AE11
AD11
AF10
TxUAddr0
TxUAddr1
TxUAddr2
TxUAddr3
TxUAddr4
AD8
TxUClav/
TxPPA
TYPE
DESCRIPTION
I
Transmit UTOPIA Address Bus:
These input pins comprise the Transmit UTOPIA Address Bus input pins. The
Transmit UTOPIA Address Bus is only in use when the XRT74L73 is operating in
the Multi-PHY mode. When the ATM Layer processor wishes to write data to a
particular UNI (PHY-Layer) device, it will provide the address of the "intended
UNI" on the Transmit UTOPIA Address Bus. The contents of the Transmit UTO-
PIA Address Bus input pins are sampled on the rising edge of TxUClk. The UNI
will compare the data on the Transmit UTOPIA Address Bus with the pre-pro-
grammed contents of the TxUT Address Register (Address = 70h). If these two
values are identical and the TxUEn pin is asserted, then the TxUClav pin will be
driven to the appropriate state (based upon the TxFIFO fill level) for the Cell
Level handshake mode of operation.
O Transmit UTOPIA Interface - Cell Available Output Pin/Transmit POS-PHY
Interface - Packet Data Available Output pin:
The exact function of this output pin depends upon whether the XRT74L73
device has been configured to operate in the ATM UNI or PPP Mode.
ATM UNI Mode - TxUClav
This output pin supports data flow control between the ATM Layer processor and
the Transmit UTOPIA Interface block. This signal is asserted (toggles "high")
when the TxFIFO is capable of receiving at least one more full cell of data from
the ATM Layer processor. This signal is negated, if the TxFIFO is not capable of
receiving one more full cell of data from the ATM Layer processor.
Multi-PHY Operation:
When the UNI chip is operating in the Multi-PHY mode, this signal will be tri-
stated until the TxUClk cycle following the assertion of a valid address on the
Transmit UTOPIA Address bus input pins (e.g., when the contents on the Trans-
mit UTOPIA Address bus pins match that within the Transmit UTOPIA Address
Register). Afterwards, this output pin will behave in accordance with the cell-
level handshake mode.
PPP Mode - TxPPA
The XRT74L73 device will drive this output pin "high" whenever a (programma-
ble) number of bytes of empty space is available (for writing more packet data)
into the TxFIFO.
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